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wdenk12b43d52005-04-05 21:57:18 +00001/*
2 * (C) Copyright 2004
3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC8220 1
32#define CONFIG_SORCERY 1 /* Sorcery board */
33
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_SYS_TEXT_BASE 0xfff00000
35
Becky Bruce31d82672008-05-08 19:02:12 -050036#define CONFIG_HIGH_BATS 1 /* High BATs supported */
37
wdenk12b43d52005-04-05 21:57:18 +000038/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
39 determine the CPU speed. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
41#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
wdenk12b43d52005-04-05 21:57:18 +000042
wdenk12b43d52005-04-05 21:57:18 +000043/*
44 * Serial console configuration
45 */
46#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
47
48#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk12b43d52005-04-05 21:57:18 +000050
wdenk7680c142005-05-16 15:23:22 +000051/* PCI */
52#define CONFIG_PCI 1
53#define CONFIG_PCI_PNP 1
54
55#define CONFIG_PCI_MEM_BUS 0x80000000
56#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57#define CONFIG_PCI_MEM_SIZE 0x10000000
58
59#define CONFIG_PCI_IO_BUS 0x71000000
60#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61#define CONFIG_PCI_IO_SIZE 0x01000000
62
63#define CONFIG_PCI_CFG_BUS 0x70000000
64#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
65#define CONFIG_PCI_CFG_SIZE 0x01000000
66
Jon Loeliger46da1e92007-07-04 22:33:30 -050067
wdenk12b43d52005-04-05 21:57:18 +000068/*
Jon Loeliger079a1362007-07-10 10:12:10 -050069 * BOOTP options
70 */
71#define CONFIG_BOOTP_BOOTFILESIZE
72#define CONFIG_BOOTP_BOOTPATH
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75
76
77/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050078 * Command line configuration.
wdenk12b43d52005-04-05 21:57:18 +000079 */
Jon Loeliger46da1e92007-07-04 22:33:30 -050080#include <config_cmd_default.h>
wdenk12b43d52005-04-05 21:57:18 +000081
Jon Loeliger46da1e92007-07-04 22:33:30 -050082#define CONFIG_CMD_BOOTD
83#define CONFIG_CMD_CACHE
84#define CONFIG_CMD_DHCP
85#define CONFIG_CMD_DIAG
86#define CONFIG_CMD_ELF
87#define CONFIG_CMD_I2C
88#define CONFIG_CMD_NET
89#define CONFIG_CMD_NFS
90#define CONFIG_CMD_PCI
91#define CONFIG_CMD_PING
92#define CONFIG_CMD_REGINFO
93#define CONFIG_CMD_SDRAM
94#define CONFIG_CMD_SNTP
wdenk12b43d52005-04-05 21:57:18 +000095
wdenk12b43d52005-04-05 21:57:18 +000096
97/*
98 * Default Environment
99 */
100#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
101#define CONFIG_HOSTNAME sorcery
102
103#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100104 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk12b43d52005-04-05 21:57:18 +0000105 "echo"
106
107#undef CONFIG_BOOTARGS
108
109#define CONFIG_EXTRA_ENV_SETTINGS \
110 "netdev=eth0\0" \
111 "nfsargs=setenv bootargs root=/dev/nfs rw " \
112 "nfsroot=$serverip:$rootpath\0" \
113 "ramargs=setenv bootargs root=/dev/ram rw\0" \
114 "addip=setenv bootargs $bootargs " \
115 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
116 ":$hostname:$netdev:off panic=1\0" \
117 "flash_nfs=run nfsargs addip;" \
118 "bootm $kernel_addr\0" \
119 "flash_self=run ramargs addip;" \
120 "bootm $kernel_addr $ramdisk_addr\0" \
121 "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
122 "rootpath=/opt/eldk/ppc_82xx\0" \
123 "bootfile=/tftpboot/sorcery/uImage\0" \
124 "kernel_addr=FFE00000\0" \
125 "ramdisk_addr=FFB00000\0" \
126 ""
127#define CONFIG_BOOTCOMMAND "run flash_self"
128
129#define CONFIG_TIMESTAMP /* Print image info with timestamp */
130
131#define CONFIG_NET_MULTI
wdenk7680c142005-05-16 15:23:22 +0000132#define CONFIG_EEPRO100
wdenk12b43d52005-04-05 21:57:18 +0000133
134/*
135 * I2C configuration
136 */
137#define CONFIG_HARD_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_I2C_MODULE 1
139#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
140#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk12b43d52005-04-05 21:57:18 +0000141
142/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_HUSH_PARSER
144#ifdef CONFIG_SYS_HUSH_PARSER
145#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk12b43d52005-04-05 21:57:18 +0000146#endif
147
148/*
149 * Flexbus Chipselect configuration
wdenk3c2b3d42005-04-05 23:32:21 +0000150 * Beware: Some CS# seem to be mandatory (if these CS# are not set,
151 * board can hang-up in unpredictable place).
wdenk12b43d52005-04-05 21:57:18 +0000152 * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
153 */
154
155/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_CS0_BASE 0xf800
157#define CONFIG_SYS_CS0_MASK 0x08000000 /* 128 MB (two chips) */
158#define CONFIG_SYS_CS0_CTRL 0x001019c0
wdenk12b43d52005-04-05 21:57:18 +0000159
160/* NVM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CS1_BASE 0xf7e8
162#define CONFIG_SYS_CS1_MASK 0x00040000 /* 256K */
163#define CONFIG_SYS_CS1_CTRL 0x00101940 /* 8bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000164
165/* Atlas2 + Gemini */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_CS2_BASE 0xf7e7
167#define CONFIG_SYS_CS2_MASK 0x00010000 /* 64K*/
168#define CONFIG_SYS_CS2_CTRL 0x001011c0 /* 16bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000169
170/* CAN Controller */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CS3_BASE 0xf7e6
172#define CONFIG_SYS_CS3_MASK 0x00010000 /* 64K */
173#define CONFIG_SYS_CS3_CTRL 0x00102140 /* 8Bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000174
175/* Foreign interface */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_CS4_BASE 0xf7e5
177#define CONFIG_SYS_CS4_MASK 0x00010000 /* 64K */
178#define CONFIG_SYS_CS4_CTRL 0x00101dc0 /* 16bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000179
wdenk7680c142005-05-16 15:23:22 +0000180/* CPLD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_CS5_BASE 0xf7e4
182#define CONFIG_SYS_CS5_MASK 0x00010000 /* 64K */
183#define CONFIG_SYS_CS5_CTRL 0x001000c0 /* 16bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
186#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_FLASH0_BASE)
wdenk12b43d52005-04-05 21:57:18 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
189#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
wdenk12b43d52005-04-05 21:57:18 +0000190
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200191#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_CFI
193#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
194 CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
wdenk12b43d52005-04-05 21:57:18 +0000195
196/*
197 * Environment settings
198 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200199#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_SIZE 0x4000 /* 16K */
202#define CONFIG_ENV_SECT_SIZE 0x20000
203#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + 0x20000)
204#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
wdenk12b43d52005-04-05 21:57:18 +0000205
206#define CONFIG_ENV_OVERWRITE 1
207
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200208#if defined CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200209#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200210#undef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200211#elif defined CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200212#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200213#undef CONFIG_ENV_IS_IN_EEPROM
214#elif defined CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200215#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200216#undef CONFIG_ENV_IS_IN_FLASH
wdenk12b43d52005-04-05 21:57:18 +0000217#endif
218
219/*
220 * Memory map
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_MBAR 0xF0000000
223#define CONFIG_SYS_SDRAM_BASE 0x00000000
224#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
225#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
226#define CONFIG_SYS_SRAM_SIZE 0x8000
wdenk12b43d52005-04-05 21:57:18 +0000227
228/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200230#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
wdenk12b43d52005-04-05 21:57:18 +0000231
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200232#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk12b43d52005-04-05 21:57:18 +0000234
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200235#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
237# define CONFIG_SYS_RAMBOOT 1
wdenk12b43d52005-04-05 21:57:18 +0000238#endif
239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
241#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
242#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk12b43d52005-04-05 21:57:18 +0000243
244/* SDRAM configuration (for SPD) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_SDRAM_TOTAL_BANKS 1
246#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
247#define CONFIG_SYS_SDRAM_SPD_SIZE 0x100
248#define CONFIG_SYS_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
wdenk12b43d52005-04-05 21:57:18 +0000249
wdenk7680c142005-05-16 15:23:22 +0000250/* SDRAM drive strength register (for SSTL_2 class II)*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
wdenk7680c142005-05-16 15:23:22 +0000252 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
253 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
254 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
255 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
256
wdenk12b43d52005-04-05 21:57:18 +0000257/*
258 * Ethernet configuration
259 */
260#define CONFIG_MPC8220_FEC 1
261#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
262#define CONFIG_PHY_ADDR 0x1F
Wolfgang Denkf60ba0d2006-09-04 02:01:27 +0200263#define CONFIG_MII 1
wdenk12b43d52005-04-05 21:57:18 +0000264
265/*
266 * Miscellaneous configurable options
267 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_LONGHELP /* undef to save memory */
269#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500270#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk12b43d52005-04-05 21:57:18 +0000272#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk12b43d52005-04-05 21:57:18 +0000274#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
276#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
277#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk12b43d52005-04-05 21:57:18 +0000278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
280#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk12b43d52005-04-05 21:57:18 +0000281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk12b43d52005-04-05 21:57:18 +0000283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk12b43d52005-04-05 21:57:18 +0000285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500287#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500289#endif
290
wdenk12b43d52005-04-05 21:57:18 +0000291/*
292 * Various low-level settings
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_HID0_INIT 0
295#define CONFIG_SYS_HID0_FINAL 0
wdenk12b43d52005-04-05 21:57:18 +0000296
wdenk7680c142005-05-16 15:23:22 +0000297/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
299#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenk7680c142005-05-16 15:23:22 +0000300*/
301
wdenk12b43d52005-04-05 21:57:18 +0000302#endif /* __CONFIG_H */