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wdenk12b43d52005-04-05 21:57:18 +00001/*
2 * (C) Copyright 2004
3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC8220 1
32#define CONFIG_SORCERY 1 /* Sorcery board */
33
34/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
35 determine the CPU speed. */
36#define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
37#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
38
39#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
40#define BOOTFLAG_WARM 0x02 /* Software reboot */
41
wdenk12b43d52005-04-05 21:57:18 +000042/*
43 * Serial console configuration
44 */
45#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
46
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49
wdenk7680c142005-05-16 15:23:22 +000050/* PCI */
51#define CONFIG_PCI 1
52#define CONFIG_PCI_PNP 1
53
54#define CONFIG_PCI_MEM_BUS 0x80000000
55#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
56#define CONFIG_PCI_MEM_SIZE 0x10000000
57
58#define CONFIG_PCI_IO_BUS 0x71000000
59#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
60#define CONFIG_PCI_IO_SIZE 0x01000000
61
62#define CONFIG_PCI_CFG_BUS 0x70000000
63#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
64#define CONFIG_PCI_CFG_SIZE 0x01000000
65
Jon Loeliger46da1e92007-07-04 22:33:30 -050066
wdenk12b43d52005-04-05 21:57:18 +000067/*
Jon Loeliger079a1362007-07-10 10:12:10 -050068 * BOOTP options
69 */
70#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74
75
76/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050077 * Command line configuration.
wdenk12b43d52005-04-05 21:57:18 +000078 */
Jon Loeliger46da1e92007-07-04 22:33:30 -050079#include <config_cmd_default.h>
wdenk12b43d52005-04-05 21:57:18 +000080
Jon Loeliger46da1e92007-07-04 22:33:30 -050081#define CONFIG_CMD_BOOTD
82#define CONFIG_CMD_CACHE
83#define CONFIG_CMD_DHCP
84#define CONFIG_CMD_DIAG
85#define CONFIG_CMD_ELF
86#define CONFIG_CMD_I2C
87#define CONFIG_CMD_NET
88#define CONFIG_CMD_NFS
89#define CONFIG_CMD_PCI
90#define CONFIG_CMD_PING
91#define CONFIG_CMD_REGINFO
92#define CONFIG_CMD_SDRAM
93#define CONFIG_CMD_SNTP
wdenk12b43d52005-04-05 21:57:18 +000094
wdenk12b43d52005-04-05 21:57:18 +000095
96/*
97 * Default Environment
98 */
99#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
100#define CONFIG_HOSTNAME sorcery
101
102#define CONFIG_PREBOOT "echo;" \
103 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
104 "echo"
105
106#undef CONFIG_BOOTARGS
107
108#define CONFIG_EXTRA_ENV_SETTINGS \
109 "netdev=eth0\0" \
110 "nfsargs=setenv bootargs root=/dev/nfs rw " \
111 "nfsroot=$serverip:$rootpath\0" \
112 "ramargs=setenv bootargs root=/dev/ram rw\0" \
113 "addip=setenv bootargs $bootargs " \
114 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
115 ":$hostname:$netdev:off panic=1\0" \
116 "flash_nfs=run nfsargs addip;" \
117 "bootm $kernel_addr\0" \
118 "flash_self=run ramargs addip;" \
119 "bootm $kernel_addr $ramdisk_addr\0" \
120 "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
121 "rootpath=/opt/eldk/ppc_82xx\0" \
122 "bootfile=/tftpboot/sorcery/uImage\0" \
123 "kernel_addr=FFE00000\0" \
124 "ramdisk_addr=FFB00000\0" \
125 ""
126#define CONFIG_BOOTCOMMAND "run flash_self"
127
128#define CONFIG_TIMESTAMP /* Print image info with timestamp */
129
130#define CONFIG_NET_MULTI
wdenk7680c142005-05-16 15:23:22 +0000131#define CONFIG_EEPRO100
wdenk12b43d52005-04-05 21:57:18 +0000132
133/*
134 * I2C configuration
135 */
136#define CONFIG_HARD_I2C 1
137#define CFG_I2C_MODULE 1
138#define CFG_I2C_SPEED 100000 /* 100 kHz */
139#define CFG_I2C_SLAVE 0x7F
140
141/* Use the HUSH parser */
142#define CFG_HUSH_PARSER
143#ifdef CFG_HUSH_PARSER
144#define CFG_PROMPT_HUSH_PS2 "> "
145#endif
146
147/*
148 * Flexbus Chipselect configuration
wdenk3c2b3d42005-04-05 23:32:21 +0000149 * Beware: Some CS# seem to be mandatory (if these CS# are not set,
150 * board can hang-up in unpredictable place).
wdenk12b43d52005-04-05 21:57:18 +0000151 * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
152 */
153
154/* Flash */
155#define CFG_CS0_BASE 0xf800
156#define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */
wdenk7680c142005-05-16 15:23:22 +0000157#define CFG_CS0_CTRL 0x001019c0
wdenk12b43d52005-04-05 21:57:18 +0000158
159/* NVM */
wdenk7680c142005-05-16 15:23:22 +0000160#define CFG_CS1_BASE 0xf7e8
161#define CFG_CS1_MASK 0x00040000 /* 256K */
162#define CFG_CS1_CTRL 0x00101940 /* 8bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000163
164/* Atlas2 + Gemini */
wdenk7680c142005-05-16 15:23:22 +0000165#define CFG_CS2_BASE 0xf7e7
166#define CFG_CS2_MASK 0x00010000 /* 64K*/
167#define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000168
169/* CAN Controller */
wdenk7680c142005-05-16 15:23:22 +0000170#define CFG_CS3_BASE 0xf7e6
wdenk12b43d52005-04-05 21:57:18 +0000171#define CFG_CS3_MASK 0x00010000 /* 64K */
wdenk7680c142005-05-16 15:23:22 +0000172#define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000173
174/* Foreign interface */
wdenk7680c142005-05-16 15:23:22 +0000175#define CFG_CS4_BASE 0xf7e5
wdenk12b43d52005-04-05 21:57:18 +0000176#define CFG_CS4_MASK 0x00010000 /* 64K */
wdenk7680c142005-05-16 15:23:22 +0000177#define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000178
wdenk7680c142005-05-16 15:23:22 +0000179/* CPLD */
180#define CFG_CS5_BASE 0xf7e4
181#define CFG_CS5_MASK 0x00010000 /* 64K */
182#define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */
wdenk12b43d52005-04-05 21:57:18 +0000183
184#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
wdenk7680c142005-05-16 15:23:22 +0000185#define CFG_FLASH_BASE (CFG_FLASH0_BASE)
wdenk12b43d52005-04-05 21:57:18 +0000186
wdenk7680c142005-05-16 15:23:22 +0000187#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
188#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
wdenk12b43d52005-04-05 21:57:18 +0000189
190#define CFG_FLASH_CFI_DRIVER
191#define CFG_FLASH_CFI
192#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
193 CFG_FLASH_BASE+0x04000000 } /* two banks */
194
195/*
196 * Environment settings
197 */
198#define CFG_ENV_IS_IN_FLASH 1
wdenk7680c142005-05-16 15:23:22 +0000199#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000)
200#define CFG_ENV_SIZE 0x4000 /* 16K */
201#define CFG_ENV_SECT_SIZE 0x20000
202#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000)
203#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
wdenk12b43d52005-04-05 21:57:18 +0000204
205#define CONFIG_ENV_OVERWRITE 1
206
207#if defined CFG_ENV_IS_IN_FLASH
208#undef CFG_ENV_IS_IN_NVRAM
209#undef CFG_ENV_IS_IN_EEPROM
210#elif defined CFG_ENV_IS_IN_NVRAM
211#undef CFG_ENV_IS_IN_FLASH
212#undef CFG_ENV_IS_IN_EEPROM
213#elif defined CFG_ENV_IS_IN_EEPROM
214#undef CFG_ENV_IS_IN_NVRAM
215#undef CFG_ENV_IS_IN_FLASH
216#endif
217
218/*
219 * Memory map
220 */
221#define CFG_MBAR 0xF0000000
222#define CFG_SDRAM_BASE 0x00000000
223#define CFG_DEFAULT_MBAR 0x80000000
224#define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
225#define CFG_SRAM_SIZE 0x8000
226
227/* Use SRAM until RAM will be available */
228#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
229#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
230
231#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
232#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
233#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
234
235#define CFG_MONITOR_BASE TEXT_BASE
236#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
237# define CFG_RAMBOOT 1
238#endif
239
240#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
241#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
242#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
243
244/* SDRAM configuration (for SPD) */
245#define CFG_SDRAM_TOTAL_BANKS 1
246#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
247#define CFG_SDRAM_SPD_SIZE 0x100
248#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
249
wdenk7680c142005-05-16 15:23:22 +0000250/* SDRAM drive strength register (for SSTL_2 class II)*/
251#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
252 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
253 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
254 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
255 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
256
wdenk12b43d52005-04-05 21:57:18 +0000257/*
258 * Ethernet configuration
259 */
260#define CONFIG_MPC8220_FEC 1
261#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
262#define CONFIG_PHY_ADDR 0x1F
Wolfgang Denkf60ba0d2006-09-04 02:01:27 +0200263#define CONFIG_MII 1
wdenk12b43d52005-04-05 21:57:18 +0000264
265/*
266 * Miscellaneous configurable options
267 */
268#define CFG_LONGHELP /* undef to save memory */
269#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500270#if defined(CONFIG_CMD_KGDB)
wdenk12b43d52005-04-05 21:57:18 +0000271#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
272#else
273#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
274#endif
275#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
276#define CFG_MAXARGS 16 /* max number of command args */
277#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
278
279#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
280#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
281
282#define CFG_LOAD_ADDR 0x100000 /* default load address */
283
284#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
285
Jon Loeliger46da1e92007-07-04 22:33:30 -0500286#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
287#if defined(CONFIG_CMD_KGDB)
288# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
289#endif
290
wdenk12b43d52005-04-05 21:57:18 +0000291/*
292 * Various low-level settings
293 */
wdenk3c2b3d42005-04-05 23:32:21 +0000294#define CFG_HID0_INIT 0
295#define CFG_HID0_FINAL 0
wdenk12b43d52005-04-05 21:57:18 +0000296
wdenk7680c142005-05-16 15:23:22 +0000297/*
298#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
299#define CFG_HID0_FINAL HID0_ICE
300*/
301
wdenk12b43d52005-04-05 21:57:18 +0000302#endif /* __CONFIG_H */