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Stefan Roese887e2ec2006-09-07 11:51:23 +02001/*
Stefan Roesee8025942007-01-30 17:06:10 +01002 * (C) Copyright 2006-2007
Stefan Roese887e2ec2006-09-07 11:51:23 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/************************************************************************
Stefan Roesee8025942007-01-30 17:06:10 +010026 * sequoia.h - configuration for Sequoia & Rainier boards
Stefan Roese887e2ec2006-09-07 11:51:23 +020027 ***********************************************************************/
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
Stefan Roesee8025942007-01-30 17:06:10 +010034/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
Stefan Roese854bc8d2006-09-13 13:51:58 +020035#ifndef CONFIG_RAINIER
Stefan Roese887e2ec2006-09-07 11:51:23 +020036#define CONFIG_440EPX 1 /* Specific PPC440EPx */
Stefan Roese854bc8d2006-09-13 13:51:58 +020037#else
38#define CONFIG_440GRX 1 /* Specific PPC440GRx */
39#endif
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020040#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese887e2ec2006-09-07 11:51:23 +020041#define CONFIG_4xx 1 /* ... PPC4xx family */
Jeffrey Manne3b8c782007-05-05 08:32:14 +020042/* Detect Sequoia PLL input clock automatically via CPLD bit */
43#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
Jeffrey Mann193b4a32007-05-07 19:42:49 +020044 33333333 : 33000000)
Stefan Roese887e2ec2006-09-07 11:51:23 +020045
46#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
47#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
48
49/*-----------------------------------------------------------------------
50 * Base addresses -- Note these are effective addresses where the
51 * actual resources get mapped (not physical addresses)
52 *----------------------------------------------------------------------*/
53#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
54#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
55
56#define CFG_BOOT_BASE_ADDR 0xf0000000
57#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
Stefan Roese4ef62512006-11-20 20:39:52 +010058#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
Stefan Roese887e2ec2006-09-07 11:51:23 +020059#define CFG_MONITOR_BASE TEXT_BASE
60#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
61#define CFG_OCM_BASE 0xe0010000 /* ocm */
Igor Lisitsina11e0692007-03-28 19:06:19 +040062#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
Stefan Roese887e2ec2006-09-07 11:51:23 +020063#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
64#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
65#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
66#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
67#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
68
69/* Don't change either of these */
70#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
71
72#define CFG_USB2D0_BASE 0xe0000100
73#define CFG_USB_DEVICE 0xe0000000
74#define CFG_USB_HOST 0xe0000400
75#define CFG_BCSR_BASE 0xc0000000
76
77/*-----------------------------------------------------------------------
78 * Initial RAM & stack pointer
79 *----------------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +020080/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Stefan Roese887e2ec2006-09-07 11:51:23 +020081#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
Stefan Roese887e2ec2006-09-07 11:51:23 +020082#define CFG_INIT_RAM_END (4 << 10)
83#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
84#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
Igor Lisitsina11e0692007-03-28 19:06:19 +040085#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
Stefan Roese887e2ec2006-09-07 11:51:23 +020086
87/*-----------------------------------------------------------------------
88 * Serial Port
89 *----------------------------------------------------------------------*/
90#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
91#define CONFIG_BAUDRATE 115200
92#define CONFIG_SERIAL_MULTI 1
93/* define this if you want console on UART1 */
94#undef CONFIG_UART1_CONSOLE
95
96#define CFG_BAUDRATE_TABLE \
97 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
98
99/*-----------------------------------------------------------------------
100 * Environment
101 *----------------------------------------------------------------------*/
Stefan Roesed12ae802006-09-12 20:19:10 +0200102#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200103#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
104#else
105#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
Stefan Roesed1a72542006-11-27 17:34:10 +0100106#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200107#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200108
109/*-----------------------------------------------------------------------
110 * FLASH related
111 *----------------------------------------------------------------------*/
112#define CFG_FLASH_CFI /* The flash is CFI compatible */
113#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
114
115#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
116
117#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
118#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
119
120#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
121#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
122
123#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
124#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
125
126#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
127#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
128
129#ifdef CFG_ENV_IS_IN_FLASH
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200130#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200131#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
132#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
133
134/* Address and size of Redundant Environment Sector */
135#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
136#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
137#endif
138
Stefan Roese887e2ec2006-09-07 11:51:23 +0200139/*
140 * IPL (Initial Program Loader, integrated inside CPU)
141 * Will load first 4k from NAND (SPL) into cache and execute it from there.
142 *
143 * SPL (Secondary Program Loader)
144 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
145 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
146 * controller and the NAND controller so that the special U-Boot image can be
147 * loaded from NAND to SDRAM.
148 *
149 * NUB (NAND U-Boot)
150 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
151 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
152 *
153 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
154 * set up. While still running from cache, I experienced problems accessing
155 * the NAND controller. sr - 2006-08-25
156 */
157#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
158#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
159#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
160#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
161#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
162#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
163
164/*
165 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
166 */
167#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
168#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
169
170/*
171 * Now the NAND chip has to be defined (no autodetection used!)
172 */
Stefan Roese9d909602007-06-01 15:29:04 +0200173#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200174#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
Stefan Roese9d909602007-06-01 15:29:04 +0200175#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
176#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200177#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
178
Stefan Roese9d909602007-06-01 15:29:04 +0200179#define CFG_NAND_ECCSIZE 256
180#define CFG_NAND_ECCBYTES 3
181#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
182#define CFG_NAND_OOBSIZE 16
183#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
184#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
185
Stefan Roese887e2ec2006-09-07 11:51:23 +0200186#ifdef CFG_ENV_IS_IN_NAND
Stefan Roesed12ae802006-09-12 20:19:10 +0200187/*
188 * For NAND booting the environment is embedded in the U-Boot image. Please take
189 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
190 */
191#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
192#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200193#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
194#endif
195
196/*-----------------------------------------------------------------------
197 * DDR SDRAM
198 *----------------------------------------------------------------------*/
Stefan Roese02388982007-01-05 10:38:05 +0100199#define CFG_MBYTES_SDRAM (256) /* 256MB */
200#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
201#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
202#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200203
204/*-----------------------------------------------------------------------
205 * I2C
206 *----------------------------------------------------------------------*/
207#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
208#undef CONFIG_SOFT_I2C /* I2C bit-banged */
209#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
210#define CFG_I2C_SLAVE 0x7F
211
212#define CFG_I2C_MULTI_EEPROMS
213#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
214#define CFG_I2C_EEPROM_ADDR_LEN 1
215#define CFG_EEPROM_PAGE_WRITE_ENABLE
216#define CFG_EEPROM_PAGE_WRITE_BITS 3
217#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
218
Stefan Roese887e2ec2006-09-07 11:51:23 +0200219/* I2C SYSMON (LM75, AD7414 is almost compatible) */
220#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
221#define CONFIG_DTT_AD7414 1 /* use AD7414 */
222#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
223#define CFG_DTT_MAX_TEMP 70
224#define CFG_DTT_LOW_TEMP -30
225#define CFG_DTT_HYSTERESIS 3
226
227#define CONFIG_PREBOOT "echo;" \
228 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
229 "echo"
230
231#undef CONFIG_BOOTARGS
232
Stefan Roesee8025942007-01-30 17:06:10 +0100233/* Setup some board specific values for the default environment variables */
234#ifndef CONFIG_RAINIER
235#define CONFIG_HOSTNAME sequoia
236#define CFG_BOOTFILE "bootfile=/tftpboot/sequoia/uImage\0"
237#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
238#else
239#define CONFIG_HOSTNAME rainier
240#define CFG_BOOTFILE "bootfile=/tftpboot/rainier/uImage\0"
241#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
242#endif
243
Stefan Roese887e2ec2006-09-07 11:51:23 +0200244#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roesee8025942007-01-30 17:06:10 +0100245 CFG_BOOTFILE \
246 CFG_ROOTPATH \
Stefan Roese887e2ec2006-09-07 11:51:23 +0200247 "netdev=eth0\0" \
Stefan Roese887e2ec2006-09-07 11:51:23 +0200248 "nfsargs=setenv bootargs root=/dev/nfs rw " \
249 "nfsroot=${serverip}:${rootpath}\0" \
250 "ramargs=setenv bootargs root=/dev/ram rw\0" \
251 "addip=setenv bootargs ${bootargs} " \
252 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
253 ":${hostname}:${netdev}:off panic=1\0" \
254 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
255 "flash_nfs=run nfsargs addip addtty;" \
256 "bootm ${kernel_addr}\0" \
257 "flash_self=run ramargs addip addtty;" \
258 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
259 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
260 "bootm\0" \
Stefan Roese4ef62512006-11-20 20:39:52 +0100261 "kernel_addr=FC000000\0" \
262 "ramdisk_addr=FC180000\0" \
Stefan Roesee8025942007-01-30 17:06:10 +0100263 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
Stefan Roese887e2ec2006-09-07 11:51:23 +0200264 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
Stefan Roesee8025942007-01-30 17:06:10 +0100265 "cp.b 200000 FFFA0000 60000\0" \
Stefan Roese887e2ec2006-09-07 11:51:23 +0200266 "upd=run load;run update\0" \
267 ""
268#define CONFIG_BOOTCOMMAND "run flash_self"
269
270#if 0
271#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
272#else
273#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
274#endif
275
276#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
277#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
278
279#define CONFIG_M88E1111_PHY 1
280#define CONFIG_IBM_EMAC4_V4 1
281#define CONFIG_MII 1 /* MII PHY management */
282#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
283
284#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
285#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
286
287#define CONFIG_HAS_ETH0
288#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
289
290#define CONFIG_NET_MULTI 1
291#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
292#define CONFIG_PHY1_ADDR 1
293
294/* USB */
Stefan Roese854bc8d2006-09-13 13:51:58 +0200295#ifdef CONFIG_440EPX
Stefan Roese887e2ec2006-09-07 11:51:23 +0200296#define CONFIG_USB_OHCI
297#define CONFIG_USB_STORAGE
298
299/* Comment this out to enable USB 1.1 device */
300#define USB_2_0_DEVICE
301
Stefan Roese854bc8d2006-09-13 13:51:58 +0200302#endif /* CONFIG_440EPX */
303
Stefan Roese887e2ec2006-09-07 11:51:23 +0200304/* Partitions */
305#define CONFIG_MAC_PARTITION
306#define CONFIG_DOS_PARTITION
307#define CONFIG_ISO_PARTITION
308
Jon Loeliger46da1e92007-07-04 22:33:30 -0500309
310/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500311 * BOOTP options
312 */
313#define CONFIG_BOOTP_BOOTFILESIZE
314#define CONFIG_BOOTP_BOOTPATH
315#define CONFIG_BOOTP_GATEWAY
316#define CONFIG_BOOTP_HOSTNAME
317
318
319/*
Jon Loeliger46da1e92007-07-04 22:33:30 -0500320 * Command line configuration.
321 */
322#include <config_cmd_default.h>
323
324#define CONFIG_CMD_ASKENV
325#define CONFIG_CMD_DHCP
326#define CONFIG_CMD_DTT
327#define CONFIG_CMD_DIAG
328#define CONFIG_CMD_EEPROM
329#define CONFIG_CMD_ELF
330#define CONFIG_CMD_FAT
331#define CONFIG_CMD_I2C
332#define CONFIG_CMD_IRQ
333#define CONFIG_CMD_MII
334#define CONFIG_CMD_NAND
335#define CONFIG_CMD_NET
336#define CONFIG_CMD_NFS
337#define CONFIG_CMD_PCI
338#define CONFIG_CMD_PING
339#define CONFIG_CMD_REGINFO
340#define CONFIG_CMD_SDRAM
341
342#ifdef CONFIG_440EPX
343#define CONFIG_CMD_USB
344#endif
345
Stefan Roese887e2ec2006-09-07 11:51:23 +0200346
Igor Lisitsina11e0692007-03-28 19:06:19 +0400347/* POST support */
348#define CONFIG_POST (CFG_POST_MEMORY | \
349 CFG_POST_CPU | \
350 CFG_POST_UART | \
351 CFG_POST_I2C | \
Sergei Poselenovb4489622007-07-05 08:17:37 +0200352 CFG_POST_CACHE | \
353 CFG_POST_FPU | \
354 CFG_POST_ETHER | \
Igor Lisitsina11e0692007-03-28 19:06:19 +0400355 CFG_POST_SPR)
356
357#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
358#define CONFIG_LOGBUFFER
Sergei Poselenovb4489622007-07-05 08:17:37 +0200359#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
Igor Lisitsina11e0692007-03-28 19:06:19 +0400360
361#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
362
Stefan Roese887e2ec2006-09-07 11:51:23 +0200363#define CONFIG_SUPPORT_VFAT
364
Stefan Roese887e2ec2006-09-07 11:51:23 +0200365/*-----------------------------------------------------------------------
366 * Miscellaneous configurable options
367 *----------------------------------------------------------------------*/
368#define CFG_LONGHELP /* undef to save memory */
369#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500370#if defined(CONFIG_CMD_KGDB)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200371#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
372#else
373#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
374#endif
375#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
376#define CFG_MAXARGS 16 /* max number of command args */
377#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
378
379#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
380#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
381
382#define CFG_LOAD_ADDR 0x100000 /* default load address */
383#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
384
385#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
386
387#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
388#define CONFIG_LOOPW 1 /* enable loopw command */
389#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
390#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
391#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
392
393/*-----------------------------------------------------------------------
394 * PCI stuff
395 *----------------------------------------------------------------------*/
396/* General PCI */
397#define CONFIG_PCI /* include pci support */
Stefan Roese23744d62007-02-01 13:22:41 +0100398#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200399#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
400#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
401
402/* Board-specific PCI */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200403#define CFG_PCI_TARGET_INIT
404#define CFG_PCI_MASTER_INIT
405
406#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
407#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
408
409/*
410 * For booting Linux, the board info and command line data
411 * have to be in the first 8 MB of memory, since this is
412 * the maximum mapped by the Linux kernel during initialization.
413 */
414#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
415
416/*-----------------------------------------------------------------------
417 * External Bus Controller (EBC) Setup
418 *----------------------------------------------------------------------*/
Stefan Roese887e2ec2006-09-07 11:51:23 +0200419
420/*
421 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
422 */
423#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
424#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
425/* Memory Bank 0 (NOR-FLASH) initialization */
Stefan Roese4be23a12007-02-19 08:23:15 +0100426#define CFG_EBC_PB0AP 0x03017200
Stefan Roese2db63362007-03-24 15:55:58 +0100427#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200428
429/* Memory Bank 3 (NAND-FLASH) initialization */
430#define CFG_EBC_PB3AP 0x018003c0
Stefan Roese2db63362007-03-24 15:55:58 +0100431#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200432#else
433#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
434/* Memory Bank 3 (NOR-FLASH) initialization */
Stefan Roese4be23a12007-02-19 08:23:15 +0100435#define CFG_EBC_PB3AP 0x03017200
Stefan Roese2db63362007-03-24 15:55:58 +0100436#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200437
438/* Memory Bank 0 (NAND-FLASH) initialization */
439#define CFG_EBC_PB0AP 0x018003c0
Stefan Roese2db63362007-03-24 15:55:58 +0100440#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200441#endif
442
443/* Memory Bank 2 (CPLD) initialization */
444#define CFG_EBC_PB2AP 0x24814580
Stefan Roese2db63362007-03-24 15:55:58 +0100445#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200446
447/*-----------------------------------------------------------------------
Stefan Roese43a2b0e2006-10-20 14:28:52 +0200448 * NAND FLASH
449 *----------------------------------------------------------------------*/
450#define CFG_MAX_NAND_DEVICE 1
451#define NAND_MAX_CHIPS 1
452#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
453#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
454
455/*-----------------------------------------------------------------------
Stefan Roese887e2ec2006-09-07 11:51:23 +0200456 * Cache Configuration
457 *----------------------------------------------------------------------*/
458#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
459#define CFG_CACHELINE_SIZE 32 /* ... */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500460#if defined(CONFIG_CMD_KGDB)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200461#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
462#endif
463
464/*
465 * Internal Definitions
466 *
467 * Boot Flags
468 */
469#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
470#define BOOTFLAG_WARM 0x02 /* Software reboot */
471
Jon Loeliger46da1e92007-07-04 22:33:30 -0500472#if defined(CONFIG_CMD_KGDB)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200473#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
474#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
475#endif
476#endif /* __CONFIG_H */