blob: 459f56878cf3078503b657439fea7aebb39fe505 [file] [log] [blame]
Heiko Schocher9acb6262006-04-20 08:42:42 +02001/*
Jens Scharsigeb0b43f2012-05-02 00:57:08 +00002 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
Heiko Schocher9acb6262006-04-20 08:42:42 +02003 *
Jens Scharsig35cf3b52009-07-24 10:31:48 +02004 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
Heiko Schocher9acb6262006-04-20 08:42:42 +02005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
Jens Scharsigeb0b43f2012-05-02 00:57:08 +000025#ifndef _CONFIG_EB_CPU5282_H_
26#define _CONFIG_EB_CPU5282_H_
Heiko Schocher9acb6262006-04-20 08:42:42 +020027
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
Wolfgang Denkb1d71352006-06-10 22:00:40 +020029
Jens Scharsig35cf3b52009-07-24 10:31:48 +020030/*----------------------------------------------------------------------*
31 * High Level Configuration Options (easy to change) *
32 *----------------------------------------------------------------------*/
Heiko Schocher9acb6262006-04-20 08:42:42 +020033
34#define CONFIG_MCF52x2 /* define processor family */
35#define CONFIG_M5282 /* define processor type */
36
37#define CONFIG_MISC_INIT_R
38
TsiChungLiew870470d2007-08-15 19:55:10 -050039#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_UART_PORT (0)
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +000041#define CONFIG_BAUDRATE 115200
Heiko Schocher9acb6262006-04-20 08:42:42 +020042
Jens Scharsig35cf3b52009-07-24 10:31:48 +020043#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
Heiko Schocher9acb6262006-04-20 08:42:42 +020044
45#define CONFIG_BOOTCOMMAND "printenv"
46
Jens Scharsig35cf3b52009-07-24 10:31:48 +020047/*----------------------------------------------------------------------*
48 * Options *
49 *----------------------------------------------------------------------*/
50
51#define CONFIG_BOOT_RETRY_TIME -1
52#define CONFIG_RESET_TO_RETRY
53#define CONFIG_SPLASH_SCREEN
54
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +000055#define CONFIG_HW_WATCHDOG
56
57#define CONFIG_STATUS_LED
58#define CONFIG_BOARD_SPECIFIC_LED
59#define STATUS_LED_ACTIVE 0
60#define STATUS_LED_BIT 0x0008 /* Timer7 GPIO */
61#define STATUS_LED_BOOT 0
62#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
63#define STATUS_LED_STATE STATUS_LED_OFF
64
Jens Scharsig35cf3b52009-07-24 10:31:48 +020065/*----------------------------------------------------------------------*
66 * Configuration for environment *
67 * Environment is in the second sector of the first 256k of flash *
68 *----------------------------------------------------------------------*/
69
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +000070#define CONFIG_ENV_ADDR 0xFF040000
71#define CONFIG_ENV_SECT_SIZE 0x00020000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020072#define CONFIG_ENV_IS_IN_FLASH 1
Heiko Schocher9acb6262006-04-20 08:42:42 +020073
Jon Loeligerdcaa7152007-07-07 20:56:05 -050074/*
Jon Loeliger11799432007-07-10 09:02:57 -050075 * BOOTP options
76 */
77#define CONFIG_BOOTP_BOOTFILESIZE
78#define CONFIG_BOOTP_BOOTPATH
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81
Jon Loeliger11799432007-07-10 09:02:57 -050082/*
Jon Loeligerdcaa7152007-07-07 20:56:05 -050083 * Command line configuration.
84 */
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +000085#define CONFIG_CMDLINE_EDITING
Jon Loeligerdcaa7152007-07-07 20:56:05 -050086#include <config_cmd_default.h>
87
88#undef CONFIG_CMD_LOADB
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +000089#define CONFIG_CMD_DATE
90#define CONFIG_CMD_DHCP
91#define CONFIG_CMD_I2C
92#define CONFIG_CMD_LED
TsiChungLiew870470d2007-08-15 19:55:10 -050093#define CONFIG_CMD_MII
94#define CONFIG_CMD_NET
Jon Loeligerdcaa7152007-07-07 20:56:05 -050095
TsiChung Liew0e0c4352008-07-09 15:21:44 -050096#define CONFIG_MCFTMR
97
Heiko Schocher9acb6262006-04-20 08:42:42 +020098#define CONFIG_BOOTDELAY 5
Jens Scharsigeb0b43f2012-05-02 00:57:08 +000099#define CONFIG_SYS_PROMPT "\nEB+CPU5282> "
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200100#define CONFIG_SYS_LONGHELP 1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200101
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200102#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200103#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
104#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
105#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Heiko Schocher9acb6262006-04-20 08:42:42 +0200106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_LOAD_ADDR 0x20000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_MEMTEST_START 0x100000
110#define CONFIG_SYS_MEMTEST_END 0x400000
111/*#define CONFIG_SYS_DRAM_TEST 1 */
112#undef CONFIG_SYS_DRAM_TEST
Heiko Schocher9acb6262006-04-20 08:42:42 +0200113
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200114/*----------------------------------------------------------------------*
115 * Clock and PLL Configuration *
116 *----------------------------------------------------------------------*/
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000117#define CONFIG_SYS_HZ 1000
118#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200119
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000120/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200121
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000122#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200123#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200124
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200125/*----------------------------------------------------------------------*
126 * Network *
127 *----------------------------------------------------------------------*/
128
129#define CONFIG_MCFFEC
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200130#define CONFIG_MII 1
131#define CONFIG_MII_INIT 1
132#define CONFIG_SYS_DISCOVER_PHY
133#define CONFIG_SYS_RX_ETH_BUFFER 8
134#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
135
136#define CONFIG_SYS_FEC0_PINMUX 0
137#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
138#define MCFFEC_TOUT_LOOP 50000
139
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200140#define CONFIG_OVERWRITE_ETHADDR_ONCE
141
142/*-------------------------------------------------------------------------
Heiko Schocher9acb6262006-04-20 08:42:42 +0200143 * Low Level Configuration Settings
144 * (address mappings, register initial values, etc.)
145 * You should know what you are doing if you make changes here.
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200146 *-----------------------------------------------------------------------*/
147
148#define CONFIG_SYS_MBAR 0x40000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200149
Heiko Schocher9acb6262006-04-20 08:42:42 +0200150/*-----------------------------------------------------------------------
151 * Definitions for initial stack pointer and data area (in DPRAM)
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200152 *-----------------------------------------------------------------------*/
153
154#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000155#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200156#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200157 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocher9acb6262006-04-20 08:42:42 +0200159
160/*-----------------------------------------------------------------------
161 * Start addresses for the final memory configuration
162 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200164 */
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000165#define CONFIG_SYS_SDRAM_BASE0 0x00000000
166#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200167
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000168#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
169#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MONITOR_LEN 0x20000
172#define CONFIG_SYS_MALLOC_LEN (256 << 10)
173#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
Heiko Schocher9acb6262006-04-20 08:42:42 +0200174
175/*
176 * For booting Linux, the board info and command line data
177 * have to be in the first 8 MB of memory, since this is
178 * the maximum mapped by the Linux kernel during initialization ??
179 */
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200180#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200181
182/*-----------------------------------------------------------------------
183 * FLASH organization
184 */
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000185#define CONFIG_FLASH_SHOW_PROGRESS 45
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200186
187#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
188#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
189#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
190
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000191#define CONFIG_SYS_MAX_FLASH_SECT 128
192#define CONFIG_SYS_MAX_FLASH_BANKS 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
194#define CONFIG_SYS_FLASH_PROTECTION
Heiko Schocher9acb6262006-04-20 08:42:42 +0200195
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000196#define CONFIG_SYS_FLASH_CFI
197#define CONFIG_FLASH_CFI_DRIVER
198#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
199#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
200
201#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
202
Heiko Schocher9acb6262006-04-20 08:42:42 +0200203/*-----------------------------------------------------------------------
204 * Cache Configuration
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_CACHELINE_SIZE 16
Heiko Schocher9acb6262006-04-20 08:42:42 +0200207
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600208#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200209 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600210#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200211 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600212#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
213#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
214 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
215 CF_ACR_EN | CF_ACR_SM_ALL)
216#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
217 CF_CACR_CEIB | CF_CACR_DBWE | \
218 CF_CACR_EUSP)
219
Heiko Schocher9acb6262006-04-20 08:42:42 +0200220/*-----------------------------------------------------------------------
221 * Memory bank definitions
222 */
223
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000224#define CONFIG_SYS_CS0_BASE 0xFF000000
TsiChung Liew012522f2008-10-21 10:03:07 +0000225#define CONFIG_SYS_CS0_CTRL 0x00001980
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000226#define CONFIG_SYS_CS0_MASK 0x00FF0001
Heiko Schocher9acb6262006-04-20 08:42:42 +0200227
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000228#define CONFIG_SYS_CS2_BASE 0xE0000000
229#define CONFIG_SYS_CS2_CTRL 0x00001980
230#define CONFIG_SYS_CS2_MASK 0x000F0001
231
232#define CONFIG_SYS_CS3_BASE 0xE0100000
233#define CONFIG_SYS_CS3_CTRL 0x00001980
TsiChung Liew012522f2008-10-21 10:03:07 +0000234#define CONFIG_SYS_CS3_MASK 0x000F0001
Heiko Schocher9acb6262006-04-20 08:42:42 +0200235
236/*-----------------------------------------------------------------------
237 * Port configuration
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
240#define CONFIG_SYS_PADDR 0x0000000
241#define CONFIG_SYS_PADAT 0x0000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
244#define CONFIG_SYS_PBDDR 0x0000000
245#define CONFIG_SYS_PBDAT 0x0000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
248#define CONFIG_SYS_PCDDR 0x0000000
249#define CONFIG_SYS_PCDAT 0x0000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
252#define CONFIG_SYS_PCDDR 0x0000000
253#define CONFIG_SYS_PCDAT 0x0000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200254
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000255#define CONFIG_SYS_PASPAR 0x0F0F
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_PEHLPAR 0xC0
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200257#define CONFIG_SYS_PUAPAR 0x0F
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_DDRUA 0x05
259#define CONFIG_SYS_PJPAR 0xFF
Heiko Schocher9acb6262006-04-20 08:42:42 +0200260
261/*-----------------------------------------------------------------------
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000262 * I2C
263 */
264
265#define CONFIG_HARD_I2C
266#define CONFIG_FSL_I2C
267
268#define CONFIG_SYS_I2C_OFFSET 0x00000300
269#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
270
271#define CONFIG_SYS_I2C_SPEED 100000
272#define CONFIG_SYS_I2C_SLAVE 0
273
274#ifdef CONFIG_CMD_DATE
275#define CONFIG_RTC_DS1338
276#define CONFIG_I2C_RTC_ADDR 0x68
277#endif
278
279/*-----------------------------------------------------------------------
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200280 * VIDEO configuration
Heiko Schocher9acb6262006-04-20 08:42:42 +0200281 */
282
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200283#define CONFIG_VIDEO
Heiko Schocher9acb6262006-04-20 08:42:42 +0200284
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200285#ifdef CONFIG_VIDEO
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000286#define CONFIG_VIDEO_VCXK 1
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200287
288#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
289#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
Jens Scharsig (BuS Elektronik)d858c332012-10-30 00:46:05 +0000290#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
Jens Scharsig35cf3b52009-07-24 10:31:48 +0200291
292#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
293#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
294#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
295
296#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
297#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
298#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
299
300#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
301#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
302#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
303
304#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
305#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
306#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
307
308#endif /* CONFIG_VIDEO */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200309#endif /* _CONFIG_M5282EVB_H */
310/*---------------------------------------------------------------------*/