blob: a13db7c2298aed0e2055e1fc334ff4e77e8bc199 [file] [log] [blame]
Heiko Schocher9acb6262006-04-20 08:42:42 +02001/*
2 * Configuation settings for the BuS EB+MCF-EV123 boards.
3 *
4 * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef _CONFIG_EB_MCF_EV123_H_
26#define _CONFIG_EB_MCF_EV123_H_
27
28#define CONFIG_EB_MCF_EV123
29
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
Wolfgang Denkb1d71352006-06-10 22:00:40 +020031
Heiko Schocher9acb6262006-04-20 08:42:42 +020032/*
33 * High Level Configuration Options (easy to change)
34 */
35
36#define CONFIG_MCF52x2 /* define processor family */
37#define CONFIG_M5282 /* define processor type */
38
39#define CONFIG_MISC_INIT_R
40
TsiChungLiew870470d2007-08-15 19:55:10 -050041#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_UART_PORT (0)
Heiko Schocher9acb6262006-04-20 08:42:42 +020043#define CONFIG_BAUDRATE 9600
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
Heiko Schocher9acb6262006-04-20 08:42:42 +020045
46#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
47
48#define CONFIG_BOOTCOMMAND "printenv"
49
50/* Configuration for environment
51 * Environment is embedded in u-boot in the second sector of the flash
52 */
53#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020054#define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */
55#define CONFIG_ENV_SECT_SIZE 0x4000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020056#define CONFIG_ENV_IS_IN_FLASH 1
Heiko Schocher9acb6262006-04-20 08:42:42 +020057/*
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020058#define CONFIG_ENV_IS_EMBEDDED 1
59#define CONFIG_ENV_ADDR_REDUND 0xF0018000
60#define CONFIG_ENV_SECT_SIZE_REDUND 0x4000
Heiko Schocher9acb6262006-04-20 08:42:42 +020061*/
62#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020063#define CONFIG_ENV_ADDR 0xFFE04000
64#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020065#define CONFIG_ENV_IS_IN_FLASH 1
Heiko Schocher9acb6262006-04-20 08:42:42 +020066#endif
67
Heiko Schocher9acb6262006-04-20 08:42:42 +020068
Jon Loeligerdcaa7152007-07-07 20:56:05 -050069/*
Jon Loeliger11799432007-07-10 09:02:57 -050070 * BOOTP options
71 */
72#define CONFIG_BOOTP_BOOTFILESIZE
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76
77
78/*
Jon Loeligerdcaa7152007-07-07 20:56:05 -050079 * Command line configuration.
80 */
81#include <config_cmd_default.h>
82
83#undef CONFIG_CMD_LOADB
TsiChungLiew870470d2007-08-15 19:55:10 -050084#define CONFIG_CMD_MII
85#define CONFIG_CMD_NET
Jon Loeligerdcaa7152007-07-07 20:56:05 -050086
TsiChung Liew0e0c4352008-07-09 15:21:44 -050087#define CONFIG_MCFTMR
88
TsiChungLiew870470d2007-08-15 19:55:10 -050089#define CONFIG_MCFFEC
90#ifdef CONFIG_MCFFEC
91# define CONFIG_NET_MULTI 1
92# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050093# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094# define CONFIG_SYS_DISCOVER_PHY
95# define CONFIG_SYS_RX_ETH_BUFFER 8
96# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew870470d2007-08-15 19:55:10 -050097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098# define CONFIG_SYS_FEC0_PINMUX 0
99# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200100# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
102# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew870470d2007-08-15 19:55:10 -0500103# define FECDUPLEX FULL
104# define FECSPEED _100BASET
105# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
107# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew870470d2007-08-15 19:55:10 -0500108# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew870470d2007-08-15 19:55:10 -0500110#endif
111
112#ifdef CONFIG_MCFFEC
113# define CONFIG_ETHADDR 00:CF:52:82:EB:01
114# define CONFIG_IPADDR 192.162.1.2
115# define CONFIG_NETMASK 255.255.255.0
116# define CONFIG_SERVERIP 192.162.1.1
117# define CONFIG_GATEWAYIP 192.162.1.1
118# define CONFIG_OVERWRITE_ETHADDR_ONCE
119#endif /* CONFIG_MCFFEC */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200120
121#define CONFIG_BOOTDELAY 5
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_PROMPT "\nEV123 U-Boot> "
123#define CONFIG_SYS_LONGHELP /* undef to save memory */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200124
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500125#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200127#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200129#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
131#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
132#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_LOAD_ADDR 0x20000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MEMTEST_START 0x100000
137#define CONFIG_SYS_MEMTEST_END 0x400000
138/*#define CONFIG_SYS_DRAM_TEST 1 */
139#undef CONFIG_SYS_DRAM_TEST
Heiko Schocher9acb6262006-04-20 08:42:42 +0200140
141/* Clock and PLL Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_HZ 10000000
143#define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200144
145/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
148#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200149
150/*
151 * Low Level Configuration Settings
152 * (address mappings, register initial values, etc.)
153 * You should know what you are doing if you make changes here.
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MBAR 0x40000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200156
Heiko Schocher9acb6262006-04-20 08:42:42 +0200157/*-----------------------------------------------------------------------
158 * Definitions for initial stack pointer and data area (in DPRAM)
159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
161#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
162#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
163#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
164#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocher9acb6262006-04-20 08:42:42 +0200165
166/*-----------------------------------------------------------------------
167 * Start addresses for the final memory configuration
168 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_SDRAM_BASE1 0x00000000
172#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200173
174/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_SDRAM_BASE0 CONFIG_SYS_SDRAM_BASE1+CONFIG_SYS_SDRAM_SIZE1*1024*1024
176#define CONFIG_SYS_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
179#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200180
TsiChung Liew012522f2008-10-21 10:03:07 +0000181#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
183#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
Heiko Schocher9acb6262006-04-20 08:42:42 +0200184
185/* If M5282 port is fully implemented the monitor base will be behind
186 * the vector table. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
188#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200189#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200191#endif
192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_MONITOR_LEN 0x20000
194#define CONFIG_SYS_MALLOC_LEN (256 << 10)
195#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
Heiko Schocher9acb6262006-04-20 08:42:42 +0200196
197/*
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization ??
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200203
204/*-----------------------------------------------------------------------
205 * FLASH organization
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_MAX_FLASH_SECT 35
208#define CONFIG_SYS_MAX_FLASH_BANKS 2
209#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
210#define CONFIG_SYS_FLASH_PROTECTION
Heiko Schocher9acb6262006-04-20 08:42:42 +0200211
212/*-----------------------------------------------------------------------
213 * Cache Configuration
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_CACHELINE_SIZE 16
Heiko Schocher9acb6262006-04-20 08:42:42 +0200216
217/*-----------------------------------------------------------------------
218 * Memory bank definitions
219 */
220
TsiChung Liew012522f2008-10-21 10:03:07 +0000221#define CONFIG_SYS_CS0_BASE 0xFFE00000
222#define CONFIG_SYS_CS0_CTRL 0x00001980
223#define CONFIG_SYS_CS0_MASK 0x001F0001
Heiko Schocher9acb6262006-04-20 08:42:42 +0200224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_CS3_BASE 0xE0000000
TsiChung Liew012522f2008-10-21 10:03:07 +0000226#define CONFIG_SYS_CS0_CTRL 0x00001980
227#define CONFIG_SYS_CS3_MASK 0x000F0001
Heiko Schocher9acb6262006-04-20 08:42:42 +0200228
229/*-----------------------------------------------------------------------
230 * Port configuration
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
233#define CONFIG_SYS_PADDR 0x0000000
234#define CONFIG_SYS_PADAT 0x0000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
237#define CONFIG_SYS_PBDDR 0x0000000
238#define CONFIG_SYS_PBDAT 0x0000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
241#define CONFIG_SYS_PCDDR 0x0000000
242#define CONFIG_SYS_PCDAT 0x0000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
245#define CONFIG_SYS_PCDDR 0x0000000
246#define CONFIG_SYS_PCDAT 0x0000000
Heiko Schocher9acb6262006-04-20 08:42:42 +0200247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_PEHLPAR 0xC0
249#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
250#define CONFIG_SYS_DDRUA 0x05
251#define CONFIG_SYS_PJPAR 0xFF
Heiko Schocher9acb6262006-04-20 08:42:42 +0200252
253/*-----------------------------------------------------------------------
254 * CCM configuration
255 */
256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_CCM_SIZ 0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200258
259/*---------------------------------------------------------------------*/
260#endif /* _CONFIG_M5282EVB_H */
261/*---------------------------------------------------------------------*/