blob: 2137282df3fd97978ec6cda00530dd4487720b55 [file] [log] [blame]
Andy Fleming063c1262011-04-08 02:10:54 -05001/*
Claudiu Manoil5be00a02013-09-30 12:44:43 +03002 * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
Andy Fleming063c1262011-04-08 02:10:54 -05003 * Jun-jie Zhang <b18070@freescale.com>
4 * Mingkai Hu <Mingkai.hu@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming063c1262011-04-08 02:10:54 -05007 */
8#ifndef __FSL_PHY_H__
9#define __FSL_PHY_H__
10
11#include <net.h>
12#include <miiphy.h>
Claudiu Manoil93f26f12014-09-05 13:52:36 +080013
14struct tsec_mii_mng {
15 u32 miimcfg; /* MII management configuration reg */
16 u32 miimcom; /* MII management command reg */
17 u32 miimadd; /* MII management address reg */
18 u32 miimcon; /* MII management control reg */
19 u32 miimstat; /* MII management status reg */
20 u32 miimind; /* MII management indication reg */
21 u32 ifstat; /* Interface Status Register */
22};
23
24int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
Andy Fleming063c1262011-04-08 02:10:54 -050025
26/* PHY register offsets */
27#define PHY_EXT_PAGE_ACCESS 0x1f
28
29/* MII Management Configuration Register */
30#define MIIMCFG_RESET_MGMT 0x80000000
31#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
32#define MIIMCFG_INIT_VALUE 0x00000003
33
34/* MII Management Command Register */
35#define MIIMCOM_READ_CYCLE 0x00000001
36#define MIIMCOM_SCAN_CYCLE 0x00000002
37
38/* MII Management Address Register */
39#define MIIMADD_PHY_ADDR_SHIFT 8
40
41/* MII Management Indicator Register */
42#define MIIMIND_BUSY 0x00000001
43#define MIIMIND_NOTVALID 0x00000004
44
Claudiu Manoil5be00a02013-09-30 12:44:43 +030045void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
Andy Fleming063c1262011-04-08 02:10:54 -050046 int dev_addr, int reg, int value);
Claudiu Manoil5be00a02013-09-30 12:44:43 +030047int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
Andy Fleming063c1262011-04-08 02:10:54 -050048 int dev_addr, int regnum);
49int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
50int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
51 u16 value);
Roy Zang111fd192012-10-08 07:44:21 +000052int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
53 int regnum, u16 value);
54int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
55 int regnum);
Andy Fleming063c1262011-04-08 02:10:54 -050056
57struct fsl_pq_mdio_info {
Claudiu Manoil5be00a02013-09-30 12:44:43 +030058 struct tsec_mii_mng __iomem *regs;
Andy Fleming063c1262011-04-08 02:10:54 -050059 char *name;
60};
61int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
62
63#endif /* __FSL_PHY_H__ */