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Andy Fleming063c1262011-04-08 02:10:54 -05001/*
Roy Zang111fd192012-10-08 07:44:21 +00002 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Andy Fleming063c1262011-04-08 02:10:54 -05003 * Jun-jie Zhang <b18070@freescale.com>
4 * Mingkai Hu <Mingkai.hu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21#ifndef __FSL_PHY_H__
22#define __FSL_PHY_H__
23
24#include <net.h>
25#include <miiphy.h>
26#include <asm/fsl_enet.h>
27
28/* PHY register offsets */
29#define PHY_EXT_PAGE_ACCESS 0x1f
30
31/* MII Management Configuration Register */
32#define MIIMCFG_RESET_MGMT 0x80000000
33#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
34#define MIIMCFG_INIT_VALUE 0x00000003
35
36/* MII Management Command Register */
37#define MIIMCOM_READ_CYCLE 0x00000001
38#define MIIMCOM_SCAN_CYCLE 0x00000002
39
40/* MII Management Address Register */
41#define MIIMADD_PHY_ADDR_SHIFT 8
42
43/* MII Management Indicator Register */
44#define MIIMIND_BUSY 0x00000001
45#define MIIMIND_NOTVALID 0x00000004
46
47void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
48 int dev_addr, int reg, int value);
49int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
50 int dev_addr, int regnum);
51int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
52int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
53 u16 value);
Roy Zang111fd192012-10-08 07:44:21 +000054int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
55 int regnum, u16 value);
56int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
57 int regnum);
Andy Fleming063c1262011-04-08 02:10:54 -050058
59struct fsl_pq_mdio_info {
60 struct tsec_mii_mng *regs;
61 char *name;
62};
63int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
64
65#endif /* __FSL_PHY_H__ */