wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * ARM Ltd. |
| 7 | * Philippe Robin, <philippe.robin@arm.com> |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | /* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ |
| 29 | /* Should be fairly simple to make it work with the PL010 as well */ |
| 30 | |
| 31 | #include <common.h> |
Stuart Wood | 8b616ed | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 32 | #include <watchdog.h> |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 33 | |
| 34 | #ifdef CFG_PL010_SERIAL |
| 35 | |
| 36 | #include "serial_pl011.h" |
| 37 | |
| 38 | #define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) |
| 39 | #define IO_READ(addr) (*(volatile unsigned int *)(addr)) |
| 40 | |
| 41 | /* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */ |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 42 | #define CONSOLE_PORT CONFIG_CONS_INDEX |
| 43 | #define baudRate CONFIG_BAUDRATE |
wdenk | 6705d81 | 2004-08-02 23:22:59 +0000 | [diff] [blame] | 44 | static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; |
| 45 | #define NUM_PORTS (sizeof(port)/sizeof(port[0])) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 46 | |
| 47 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 48 | static void pl010_putc (int portnum, char c); |
| 49 | static int pl010_getc (int portnum); |
| 50 | static int pl010_tstc (int portnum); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 51 | |
| 52 | |
| 53 | int serial_init (void) |
| 54 | { |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 55 | unsigned int divisor; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 56 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 57 | /* |
| 58 | ** First, disable everything. |
| 59 | */ |
| 60 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 61 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 62 | /* |
| 63 | ** Set baud rate |
| 64 | ** |
| 65 | */ |
| 66 | switch (baudRate) { |
| 67 | case 9600: |
| 68 | divisor = UART_PL010_BAUD_9600; |
| 69 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 70 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 71 | case 19200: |
| 72 | divisor = UART_PL010_BAUD_9600; |
| 73 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 74 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 75 | case 38400: |
| 76 | divisor = UART_PL010_BAUD_38400; |
| 77 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 78 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 79 | case 57600: |
| 80 | divisor = UART_PL010_BAUD_57600; |
| 81 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 82 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 83 | case 115200: |
| 84 | divisor = UART_PL010_BAUD_115200; |
| 85 | break; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 86 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 87 | default: |
| 88 | divisor = UART_PL010_BAUD_38400; |
| 89 | } |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 90 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 91 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, |
| 92 | ((divisor & 0xf00) >> 8)); |
| 93 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 94 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 95 | /* |
| 96 | ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. |
| 97 | */ |
| 98 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, |
| 99 | (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 100 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 101 | /* |
| 102 | ** Finally, enable the UART |
| 103 | */ |
| 104 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); |
| 105 | |
| 106 | return (0); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 107 | } |
| 108 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 109 | void serial_putc (const char c) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 110 | { |
| 111 | if (c == '\n') |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 112 | pl010_putc (CONSOLE_PORT, '\r'); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 113 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 114 | pl010_putc (CONSOLE_PORT, c); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 115 | } |
| 116 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 117 | void serial_puts (const char *s) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 118 | { |
| 119 | while (*s) { |
| 120 | serial_putc (*s++); |
| 121 | } |
| 122 | } |
| 123 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 124 | int serial_getc (void) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 125 | { |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 126 | return pl010_getc (CONSOLE_PORT); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 127 | } |
| 128 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 129 | int serial_tstc (void) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 130 | { |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 131 | return pl010_tstc (CONSOLE_PORT); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 132 | } |
| 133 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 134 | void serial_setbrg (void) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 135 | { |
| 136 | } |
| 137 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 138 | static void pl010_putc (int portnum, char c) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 139 | { |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 140 | /* Wait until there is space in the FIFO */ |
Stuart Wood | 8b616ed | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 141 | while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF) |
| 142 | WATCHDOG_RESET(); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 143 | |
| 144 | /* Send the character */ |
| 145 | IO_WRITE (port[portnum] + UART_PL01x_DR, c); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 146 | } |
| 147 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 148 | static int pl010_getc (int portnum) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 149 | { |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 150 | unsigned int data; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 151 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 152 | /* Wait until there is data in the FIFO */ |
Stuart Wood | 8b616ed | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 153 | while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE) |
| 154 | WATCHDOG_RESET(); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 155 | |
| 156 | data = IO_READ (port[portnum] + UART_PL01x_DR); |
| 157 | |
| 158 | /* Check for an error flag */ |
| 159 | if (data & 0xFFFFFF00) { |
| 160 | /* Clear the error */ |
| 161 | IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); |
| 162 | return -1; |
| 163 | } |
| 164 | |
| 165 | return (int) data; |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 166 | } |
| 167 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 168 | static int pl010_tstc (int portnum) |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 169 | { |
Stuart Wood | 8b616ed | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 170 | WATCHDOG_RESET(); |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 171 | return !(IO_READ (port[portnum] + UART_PL01x_FR) & |
| 172 | UART_PL01x_FR_RXFE); |
wdenk | 3d3befa | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | #endif |