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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * (C) Copyright 2004
6 * ARM Ltd.
7 * Philippe Robin, <philippe.robin@arm.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */
29/* Should be fairly simple to make it work with the PL010 as well */
30
31#include <common.h>
Stuart Wood8b616ed2008-06-02 16:42:19 -040032#include <watchdog.h>
wdenk3d3befa2004-03-14 15:06:13 +000033
34#ifdef CFG_PL010_SERIAL
35
36#include "serial_pl011.h"
37
38#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
39#define IO_READ(addr) (*(volatile unsigned int *)(addr))
40
41/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */
wdenk3d3befa2004-03-14 15:06:13 +000042#define CONSOLE_PORT CONFIG_CONS_INDEX
43#define baudRate CONFIG_BAUDRATE
wdenk6705d812004-08-02 23:22:59 +000044static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
45#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
wdenk3d3befa2004-03-14 15:06:13 +000046
47
wdenk42dfe7a2004-03-14 22:25:36 +000048static void pl010_putc (int portnum, char c);
49static int pl010_getc (int portnum);
50static int pl010_tstc (int portnum);
wdenk3d3befa2004-03-14 15:06:13 +000051
52
53int serial_init (void)
54{
wdenk42dfe7a2004-03-14 22:25:36 +000055 unsigned int divisor;
wdenk3d3befa2004-03-14 15:06:13 +000056
wdenk42dfe7a2004-03-14 22:25:36 +000057 /*
58 ** First, disable everything.
59 */
60 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
wdenk3d3befa2004-03-14 15:06:13 +000061
wdenk42dfe7a2004-03-14 22:25:36 +000062 /*
63 ** Set baud rate
64 **
65 */
66 switch (baudRate) {
67 case 9600:
68 divisor = UART_PL010_BAUD_9600;
69 break;
wdenk3d3befa2004-03-14 15:06:13 +000070
wdenk42dfe7a2004-03-14 22:25:36 +000071 case 19200:
72 divisor = UART_PL010_BAUD_9600;
73 break;
wdenk3d3befa2004-03-14 15:06:13 +000074
wdenk42dfe7a2004-03-14 22:25:36 +000075 case 38400:
76 divisor = UART_PL010_BAUD_38400;
77 break;
wdenk3d3befa2004-03-14 15:06:13 +000078
wdenk42dfe7a2004-03-14 22:25:36 +000079 case 57600:
80 divisor = UART_PL010_BAUD_57600;
81 break;
wdenk3d3befa2004-03-14 15:06:13 +000082
wdenk42dfe7a2004-03-14 22:25:36 +000083 case 115200:
84 divisor = UART_PL010_BAUD_115200;
85 break;
wdenk3d3befa2004-03-14 15:06:13 +000086
wdenk42dfe7a2004-03-14 22:25:36 +000087 default:
88 divisor = UART_PL010_BAUD_38400;
89 }
wdenk3d3befa2004-03-14 15:06:13 +000090
wdenk42dfe7a2004-03-14 22:25:36 +000091 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM,
92 ((divisor & 0xf00) >> 8));
93 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
wdenk3d3befa2004-03-14 15:06:13 +000094
wdenk42dfe7a2004-03-14 22:25:36 +000095 /*
96 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
97 */
98 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH,
99 (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
wdenk3d3befa2004-03-14 15:06:13 +0000100
wdenk42dfe7a2004-03-14 22:25:36 +0000101 /*
102 ** Finally, enable the UART
103 */
104 IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
105
106 return (0);
wdenk3d3befa2004-03-14 15:06:13 +0000107}
108
wdenk42dfe7a2004-03-14 22:25:36 +0000109void serial_putc (const char c)
wdenk3d3befa2004-03-14 15:06:13 +0000110{
111 if (c == '\n')
wdenk42dfe7a2004-03-14 22:25:36 +0000112 pl010_putc (CONSOLE_PORT, '\r');
wdenk3d3befa2004-03-14 15:06:13 +0000113
wdenk42dfe7a2004-03-14 22:25:36 +0000114 pl010_putc (CONSOLE_PORT, c);
wdenk3d3befa2004-03-14 15:06:13 +0000115}
116
wdenk42dfe7a2004-03-14 22:25:36 +0000117void serial_puts (const char *s)
wdenk3d3befa2004-03-14 15:06:13 +0000118{
119 while (*s) {
120 serial_putc (*s++);
121 }
122}
123
wdenk42dfe7a2004-03-14 22:25:36 +0000124int serial_getc (void)
wdenk3d3befa2004-03-14 15:06:13 +0000125{
wdenk42dfe7a2004-03-14 22:25:36 +0000126 return pl010_getc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000127}
128
wdenk42dfe7a2004-03-14 22:25:36 +0000129int serial_tstc (void)
wdenk3d3befa2004-03-14 15:06:13 +0000130{
wdenk42dfe7a2004-03-14 22:25:36 +0000131 return pl010_tstc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000132}
133
wdenk42dfe7a2004-03-14 22:25:36 +0000134void serial_setbrg (void)
wdenk3d3befa2004-03-14 15:06:13 +0000135{
136}
137
wdenk42dfe7a2004-03-14 22:25:36 +0000138static void pl010_putc (int portnum, char c)
wdenk3d3befa2004-03-14 15:06:13 +0000139{
wdenk42dfe7a2004-03-14 22:25:36 +0000140 /* Wait until there is space in the FIFO */
Stuart Wood8b616ed2008-06-02 16:42:19 -0400141 while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
142 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000143
144 /* Send the character */
145 IO_WRITE (port[portnum] + UART_PL01x_DR, c);
wdenk3d3befa2004-03-14 15:06:13 +0000146}
147
wdenk42dfe7a2004-03-14 22:25:36 +0000148static int pl010_getc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000149{
wdenk42dfe7a2004-03-14 22:25:36 +0000150 unsigned int data;
wdenk3d3befa2004-03-14 15:06:13 +0000151
wdenk42dfe7a2004-03-14 22:25:36 +0000152 /* Wait until there is data in the FIFO */
Stuart Wood8b616ed2008-06-02 16:42:19 -0400153 while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE)
154 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000155
156 data = IO_READ (port[portnum] + UART_PL01x_DR);
157
158 /* Check for an error flag */
159 if (data & 0xFFFFFF00) {
160 /* Clear the error */
161 IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
162 return -1;
163 }
164
165 return (int) data;
wdenk3d3befa2004-03-14 15:06:13 +0000166}
167
wdenk42dfe7a2004-03-14 22:25:36 +0000168static int pl010_tstc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000169{
Stuart Wood8b616ed2008-06-02 16:42:19 -0400170 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000171 return !(IO_READ (port[portnum] + UART_PL01x_FR) &
172 UART_PL01x_FR_RXFE);
wdenk3d3befa2004-03-14 15:06:13 +0000173}
174
175#endif