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wdenk10a36a92004-07-10 23:02:23 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8560 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/* mpc8560ads board configuration file */
28/* please refer to doc/README.mpc85xx for more info */
29/* make sure you change the MAC address and other network params first,
30 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/* High Level Configuration Options */
37#define CONFIG_BOOKE 1 /* BOOKE */
38#define CONFIG_E500 1 /* BOOKE e500 family */
39#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
40#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
41
42
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050043#define CONFIG_CPM2 1 /* has CPM2 */
wdenk10a36a92004-07-10 23:02:23 +000044#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
45
46/* XXX flagging this as something I might want to delete */
47#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
48
49#define CONFIG_TSEC_ENET /* tsec ethernet support */
50#undef CONFIG_PCI /* pci ethernet support */
51#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
52
Kumar Galae2b159d2008-01-16 09:05:27 -060053#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk10a36a92004-07-10 23:02:23 +000054
55#define CONFIG_ENV_OVERWRITE
56
57/* Using Localbus SDRAM to emulate flash before we can program the flash,
58 * normally you need a flash-boot image(u-boot.bin), if so undef this.
59 */
60#undef CONFIG_RAM_AS_FLASH
61
62#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
63 #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
64#else
65 #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
66#endif
67
68/* below can be toggled for performance analysis. otherwise use default */
69#define CONFIG_L2_CACHE /* toggle L2 cache */
70#undef CONFIG_BTB /* toggle branch predition */
71#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
72
73#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
74
75#undef CFG_DRAM_TEST /* memory test, takes time */
76#define CFG_MEMTEST_START 0x00200000 /* memtest region */
77#define CFG_MEMTEST_END 0x00400000
78
79#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
80 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
81 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
82#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
83#endif
84
85/*
86 * Base addresses -- Note these are effective addresses where the
87 * actual resources get mapped (not physical addresses)
88 */
89#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
90
91#if XXX
92 #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
93#else
94 #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
95#endif
Kumar Galaf69766e2008-01-30 14:55:14 -060096#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
wdenk10a36a92004-07-10 23:02:23 +000097#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
98
99#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
100#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
101#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
102#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
103
104#undef CONFIG_DDR_ECC /* only for ECC DDR module */
105#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
106
107#if defined(CONFIG_MPC85xx_REV1)
108 #define CONFIG_DDR_DLL /* possible DLL fix needed */
109#endif
110
111#undef CONFIG_CLOCKS_IN_MHZ
112
113#if defined(CONFIG_RAM_AS_FLASH)
114 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
115 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
116 #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
117 #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
118#else /* Boot from real Flash */
119 #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
120 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
121 #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
122 #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
123#endif
124#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
125
126/* local bus definitions */
127#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
128#define CFG_OR1_PRELIM 0xfc000ff7
129
130#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
131#define CFG_OR2_PRELIM 0x00000000
132
133#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
134#define CFG_OR3_PRELIM 0xfc000cc1
135
136#if defined(CONFIG_RAM_AS_FLASH)
137 #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
138#else
139 #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
140#endif
141#define CFG_OR4_PRELIM 0xfc000cc1
142
143#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
144#if 1
145 #define CFG_OR5_PRELIM 0xff000ff7
146#else
147 #define CFG_OR5_PRELIM 0xff0000f0
148#endif
149
150#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
151#define CFG_OR6_PRELIM 0xfc000ff7
152#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
153#define CFG_LBC_LBCR 0x00000000
154#define CFG_LBC_LSRT 0x20000000
155#define CFG_LBC_MRTPR 0x20000000
156#define CFG_LBC_LSDMR_1 0x2861b723
157#define CFG_LBC_LSDMR_2 0x0861b723
158#define CFG_LBC_LSDMR_3 0x0861b723
159#define CFG_LBC_LSDMR_4 0x1861b723
160#define CFG_LBC_LSDMR_5 0x4061b723
161
162/* just hijack the MOT BCSR def for SBC8560 misc devices */
163#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
164/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
165
166#define CONFIG_L1_INIT_RAM
167#define CFG_INIT_RAM_LOCK 1
168#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
169#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
170
171#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
172#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
173#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
174
175#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
176#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
177
178/* Serial Port */
179#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
180#undef CONFIG_CONS_NONE /* define if console on something else */
181
182#define CONFIG_CONS_INDEX 1
183#undef CONFIG_SERIAL_SOFTWARE_FIFO
184#define CFG_NS16550
185#define CFG_NS16550_SERIAL
186#define CFG_NS16550_REG_SIZE 1
187#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
188#define CONFIG_BAUDRATE 9600
189
190#define CFG_BAUDRATE_TABLE \
191 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
192
193#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
194#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
195
196/* Use the HUSH parser */
197#define CFG_HUSH_PARSER
198#ifdef CFG_HUSH_PARSER
199#define CFG_PROMPT_HUSH_PS2 "> "
200#endif
201
Jon Loeliger20476722006-10-20 15:50:15 -0500202/*
203 * I2C
204 */
205#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
206#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk10a36a92004-07-10 23:02:23 +0000207#undef CONFIG_SOFT_I2C /* I2C bit-banged */
208#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
209#define CFG_I2C_SLAVE 0x7F
210#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500211#define CFG_I2C_OFFSET 0x3000
wdenk10a36a92004-07-10 23:02:23 +0000212
213#define CFG_PCI_MEM_BASE 0xC0000000
214#define CFG_PCI_MEM_PHYS 0xC0000000
215#define CFG_PCI_MEM_SIZE 0x10000000
216
217#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
218
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500219# define CONFIG_NET_MULTI 1
220# define CONFIG_MII 1 /* MII PHY management */
221# define CONFIG_MPC85xx_TSEC1
222# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
223# define TSEC1_PHY_ADDR 25
224# define TSEC1_PHYIDX 0
225/* Options are: TSEC0 */
226# define CONFIG_ETHPRIME "TSEC0"
wdenk10a36a92004-07-10 23:02:23 +0000227
228#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
229
230 #undef CONFIG_ETHER_NONE /* define if ether on something else */
231 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
232 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
233
234 #if (CONFIG_ETHER_INDEX == 2)
235 /*
236 * - Rx-CLK is CLK13
237 * - Tx-CLK is CLK14
238 * - Select bus for bd/buffers
239 * - Full duplex
240 */
241 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
242 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
243 #define CFG_CPMFCR_RAMTYPE 0
244 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
245
246 #elif (CONFIG_ETHER_INDEX == 3)
247 /* need more definitions here for FE3 */
248 #endif /* CONFIG_ETHER_INDEX */
249
250 #define CONFIG_MII /* MII PHY management */
251 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
252 /*
253 * GPIO pins used for bit-banged MII communications
254 */
255 #define MDIO_PORT 2 /* Port C */
256 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
257 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
258 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
259
260 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
261 else iop->pdat &= ~0x00400000
262
263 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
264 else iop->pdat &= ~0x00200000
265
266 #define MIIDELAY udelay(1)
267
268#endif
269
270/*-----------------------------------------------------------------------
271 * FLASH and environment organization
272 */
273
274#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
275#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
276#if 0
277#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
278#define CFG_FLASH_PROTECTION /* use hardware protection */
279#endif
280#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
281#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
282
283#undef CFG_FLASH_CHECKSUM
284#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
285#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
286
287#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
288
289#if 0
290/* XXX This doesn't work and I don't want to fix it */
291#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
292 #define CFG_RAMBOOT
293#else
294 #undef CFG_RAMBOOT
295#endif
296#endif
297
298/* Environment */
299#if !defined(CFG_RAMBOOT)
300 #if defined(CONFIG_RAM_AS_FLASH)
301 #define CFG_ENV_IS_NOWHERE
302 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
303 #define CFG_ENV_SIZE 0x2000
304 #else
305 #define CFG_ENV_IS_IN_FLASH 1
306 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
307 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
308 #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
309 #endif
310#else
311 #define CFG_NO_FLASH 1 /* Flash is not usable now */
312 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
313 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
314 #define CFG_ENV_SIZE 0x2000
315#endif
316
317#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
318/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
319#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
320#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
321
322#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
323#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
324
Jon Loeliger2835e512007-06-13 13:22:08 -0500325
326/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500327 * BOOTP options
328 */
329#define CONFIG_BOOTP_BOOTFILESIZE
330#define CONFIG_BOOTP_BOOTPATH
331#define CONFIG_BOOTP_GATEWAY
332#define CONFIG_BOOTP_HOSTNAME
333
334
335/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500336 * Command line configuration.
337 */
338#include <config_cmd_default.h>
339
340#define CONFIG_CMD_PING
341#define CONFIG_CMD_I2C
342
343#if defined(CONFIG_PCI)
344 #define CONFIG_CMD_PCI
wdenk10a36a92004-07-10 23:02:23 +0000345#endif
346
Jon Loeliger2835e512007-06-13 13:22:08 -0500347#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
348 #define CONFIG_CMD_MII
349#endif
350
351#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
352 #undef CONFIG_CMD_ENV
353 #undef CONFIG_CMD_LOADS
354#endif
355
wdenk10a36a92004-07-10 23:02:23 +0000356
357#undef CONFIG_WATCHDOG /* watchdog disabled */
358
359/*
360 * Miscellaneous configurable options
361 */
362#define CFG_LONGHELP /* undef to save memory */
363#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500364#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000365 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
366#else
367 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
368#endif
369#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
370#define CFG_MAXARGS 16 /* max number of command args */
371#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
372#define CFG_LOAD_ADDR 0x1000000 /* default load address */
373#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
374
375/*
376 * For booting Linux, the board info and command line data
377 * have to be in the first 8 MB of memory, since this is
378 * the maximum mapped by the Linux kernel during initialization.
379 */
380#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
381
wdenk10a36a92004-07-10 23:02:23 +0000382/*
383 * Internal Definitions
384 *
385 * Boot Flags
386 */
387#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
388#define BOOTFLAG_WARM 0x02 /* Software reboot */
389
Jon Loeliger2835e512007-06-13 13:22:08 -0500390#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000391 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
392 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
393#endif
394
395/*Note: change below for your network setting!!! */
396#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000397# define CONFIG_ETHADDR 00:01:af:07:9b:8a
398# define CONFIG_HAS_ETH1
399# define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
400# define CONFIG_HAS_ETH2
401# define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
wdenk10a36a92004-07-10 23:02:23 +0000402#endif
403
404#define CONFIG_SERVERIP 192.168.0.131
405#define CONFIG_IPADDR 192.168.0.105
406#define CONFIG_GATEWAYIP 0.0.0.0
407#define CONFIG_NETMASK 255.255.255.0
408#define CONFIG_HOSTNAME SBC8560
409#define CONFIG_ROOTPATH /home/ppc
410#define CONFIG_BOOTFILE pImage
411
412#endif /* __CONFIG_H */