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wdenk10a36a92004-07-10 23:02:23 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8560 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/* mpc8560ads board configuration file */
28/* please refer to doc/README.mpc85xx for more info */
29/* make sure you change the MAC address and other network params first,
30 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/* High Level Configuration Options */
37#define CONFIG_BOOKE 1 /* BOOKE */
38#define CONFIG_E500 1 /* BOOKE e500 family */
39#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
40#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
41
42
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050043#define CONFIG_CPM2 1 /* has CPM2 */
wdenk10a36a92004-07-10 23:02:23 +000044#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
45
46/* XXX flagging this as something I might want to delete */
47#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
48
49#define CONFIG_TSEC_ENET /* tsec ethernet support */
50#undef CONFIG_PCI /* pci ethernet support */
51#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
52
53
54#define CONFIG_ENV_OVERWRITE
55
56/* Using Localbus SDRAM to emulate flash before we can program the flash,
57 * normally you need a flash-boot image(u-boot.bin), if so undef this.
58 */
59#undef CONFIG_RAM_AS_FLASH
60
61#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
62 #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
63#else
64 #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
65#endif
66
67/* below can be toggled for performance analysis. otherwise use default */
68#define CONFIG_L2_CACHE /* toggle L2 cache */
69#undef CONFIG_BTB /* toggle branch predition */
70#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
71
72#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
73
74#undef CFG_DRAM_TEST /* memory test, takes time */
75#define CFG_MEMTEST_START 0x00200000 /* memtest region */
76#define CFG_MEMTEST_END 0x00400000
77
78#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
79 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
80 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
81#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
82#endif
83
84/*
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
87 */
88#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89
90#if XXX
91 #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
92#else
93 #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
94#endif
95#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
96
97#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
98#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
99#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
100#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
101
102#undef CONFIG_DDR_ECC /* only for ECC DDR module */
103#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
104
105#if defined(CONFIG_MPC85xx_REV1)
106 #define CONFIG_DDR_DLL /* possible DLL fix needed */
107#endif
108
109#undef CONFIG_CLOCKS_IN_MHZ
110
111#if defined(CONFIG_RAM_AS_FLASH)
112 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
113 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
114 #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
115 #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
116#else /* Boot from real Flash */
117 #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
118 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
119 #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
120 #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
121#endif
122#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
123
124/* local bus definitions */
125#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
126#define CFG_OR1_PRELIM 0xfc000ff7
127
128#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
129#define CFG_OR2_PRELIM 0x00000000
130
131#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
132#define CFG_OR3_PRELIM 0xfc000cc1
133
134#if defined(CONFIG_RAM_AS_FLASH)
135 #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
136#else
137 #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
138#endif
139#define CFG_OR4_PRELIM 0xfc000cc1
140
141#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
142#if 1
143 #define CFG_OR5_PRELIM 0xff000ff7
144#else
145 #define CFG_OR5_PRELIM 0xff0000f0
146#endif
147
148#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
149#define CFG_OR6_PRELIM 0xfc000ff7
150#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
151#define CFG_LBC_LBCR 0x00000000
152#define CFG_LBC_LSRT 0x20000000
153#define CFG_LBC_MRTPR 0x20000000
154#define CFG_LBC_LSDMR_1 0x2861b723
155#define CFG_LBC_LSDMR_2 0x0861b723
156#define CFG_LBC_LSDMR_3 0x0861b723
157#define CFG_LBC_LSDMR_4 0x1861b723
158#define CFG_LBC_LSDMR_5 0x4061b723
159
160/* just hijack the MOT BCSR def for SBC8560 misc devices */
161#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
162/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
163
164#define CONFIG_L1_INIT_RAM
165#define CFG_INIT_RAM_LOCK 1
166#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
167#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
168
169#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
170#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
171#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
172
173#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
174#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
175
176/* Serial Port */
177#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
178#undef CONFIG_CONS_NONE /* define if console on something else */
179
180#define CONFIG_CONS_INDEX 1
181#undef CONFIG_SERIAL_SOFTWARE_FIFO
182#define CFG_NS16550
183#define CFG_NS16550_SERIAL
184#define CFG_NS16550_REG_SIZE 1
185#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
186#define CONFIG_BAUDRATE 9600
187
188#define CFG_BAUDRATE_TABLE \
189 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
190
191#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
192#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
193
194/* Use the HUSH parser */
195#define CFG_HUSH_PARSER
196#ifdef CFG_HUSH_PARSER
197#define CFG_PROMPT_HUSH_PS2 "> "
198#endif
199
Jon Loeliger20476722006-10-20 15:50:15 -0500200/*
201 * I2C
202 */
203#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
204#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk10a36a92004-07-10 23:02:23 +0000205#undef CONFIG_SOFT_I2C /* I2C bit-banged */
206#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
207#define CFG_I2C_SLAVE 0x7F
208#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500209#define CFG_I2C_OFFSET 0x3000
wdenk10a36a92004-07-10 23:02:23 +0000210
211#define CFG_PCI_MEM_BASE 0xC0000000
212#define CFG_PCI_MEM_PHYS 0xC0000000
213#define CFG_PCI_MEM_SIZE 0x10000000
214
215#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
216
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500217# define CONFIG_NET_MULTI 1
218# define CONFIG_MII 1 /* MII PHY management */
219# define CONFIG_MPC85xx_TSEC1
220# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
221# define TSEC1_PHY_ADDR 25
222# define TSEC1_PHYIDX 0
223/* Options are: TSEC0 */
224# define CONFIG_ETHPRIME "TSEC0"
wdenk10a36a92004-07-10 23:02:23 +0000225
226#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
227
228 #undef CONFIG_ETHER_NONE /* define if ether on something else */
229 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
230 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
231
232 #if (CONFIG_ETHER_INDEX == 2)
233 /*
234 * - Rx-CLK is CLK13
235 * - Tx-CLK is CLK14
236 * - Select bus for bd/buffers
237 * - Full duplex
238 */
239 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
240 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
241 #define CFG_CPMFCR_RAMTYPE 0
242 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
243
244 #elif (CONFIG_ETHER_INDEX == 3)
245 /* need more definitions here for FE3 */
246 #endif /* CONFIG_ETHER_INDEX */
247
248 #define CONFIG_MII /* MII PHY management */
249 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
250 /*
251 * GPIO pins used for bit-banged MII communications
252 */
253 #define MDIO_PORT 2 /* Port C */
254 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
255 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
256 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
257
258 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
259 else iop->pdat &= ~0x00400000
260
261 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
262 else iop->pdat &= ~0x00200000
263
264 #define MIIDELAY udelay(1)
265
266#endif
267
268/*-----------------------------------------------------------------------
269 * FLASH and environment organization
270 */
271
272#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
273#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
274#if 0
275#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
276#define CFG_FLASH_PROTECTION /* use hardware protection */
277#endif
278#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
279#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
280
281#undef CFG_FLASH_CHECKSUM
282#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
283#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
284
285#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
286
287#if 0
288/* XXX This doesn't work and I don't want to fix it */
289#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
290 #define CFG_RAMBOOT
291#else
292 #undef CFG_RAMBOOT
293#endif
294#endif
295
296/* Environment */
297#if !defined(CFG_RAMBOOT)
298 #if defined(CONFIG_RAM_AS_FLASH)
299 #define CFG_ENV_IS_NOWHERE
300 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
301 #define CFG_ENV_SIZE 0x2000
302 #else
303 #define CFG_ENV_IS_IN_FLASH 1
304 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
305 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
306 #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
307 #endif
308#else
309 #define CFG_NO_FLASH 1 /* Flash is not usable now */
310 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
311 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
312 #define CFG_ENV_SIZE 0x2000
313#endif
314
315#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
316/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
317#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
318#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
319
320#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
321#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
322
Jon Loeliger2835e512007-06-13 13:22:08 -0500323
324/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500325 * BOOTP options
326 */
327#define CONFIG_BOOTP_BOOTFILESIZE
328#define CONFIG_BOOTP_BOOTPATH
329#define CONFIG_BOOTP_GATEWAY
330#define CONFIG_BOOTP_HOSTNAME
331
332
333/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500334 * Command line configuration.
335 */
336#include <config_cmd_default.h>
337
338#define CONFIG_CMD_PING
339#define CONFIG_CMD_I2C
340
341#if defined(CONFIG_PCI)
342 #define CONFIG_CMD_PCI
wdenk10a36a92004-07-10 23:02:23 +0000343#endif
344
Jon Loeliger2835e512007-06-13 13:22:08 -0500345#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
346 #define CONFIG_CMD_MII
347#endif
348
349#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
350 #undef CONFIG_CMD_ENV
351 #undef CONFIG_CMD_LOADS
352#endif
353
wdenk10a36a92004-07-10 23:02:23 +0000354
355#undef CONFIG_WATCHDOG /* watchdog disabled */
356
357/*
358 * Miscellaneous configurable options
359 */
360#define CFG_LONGHELP /* undef to save memory */
361#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500362#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000363 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
364#else
365 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
366#endif
367#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
368#define CFG_MAXARGS 16 /* max number of command args */
369#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
370#define CFG_LOAD_ADDR 0x1000000 /* default load address */
371#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
372
373/*
374 * For booting Linux, the board info and command line data
375 * have to be in the first 8 MB of memory, since this is
376 * the maximum mapped by the Linux kernel during initialization.
377 */
378#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
379
380/* Cache Configuration */
381#define CFG_DCACHE_SIZE 32768
382#define CFG_CACHELINE_SIZE 32
Jon Loeliger2835e512007-06-13 13:22:08 -0500383#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000384 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
385#endif
386
387/*
388 * Internal Definitions
389 *
390 * Boot Flags
391 */
392#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
393#define BOOTFLAG_WARM 0x02 /* Software reboot */
394
Jon Loeliger2835e512007-06-13 13:22:08 -0500395#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000396 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
397 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
398#endif
399
400/*Note: change below for your network setting!!! */
401#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000402# define CONFIG_ETHADDR 00:01:af:07:9b:8a
403# define CONFIG_HAS_ETH1
404# define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
405# define CONFIG_HAS_ETH2
406# define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
wdenk10a36a92004-07-10 23:02:23 +0000407#endif
408
409#define CONFIG_SERVERIP 192.168.0.131
410#define CONFIG_IPADDR 192.168.0.105
411#define CONFIG_GATEWAYIP 0.0.0.0
412#define CONFIG_NETMASK 255.255.255.0
413#define CONFIG_HOSTNAME SBC8560
414#define CONFIG_ROOTPATH /home/ppc
415#define CONFIG_BOOTFILE pImage
416
417#endif /* __CONFIG_H */