blob: ff4ebfb4447f9452b5e71d75b2ad5e068b440570 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302/**
3 * dwc3-omap.c - OMAP Specific Glue layer
4 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +05305 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05306 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +053010 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported
11 * to uboot.
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053012 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +053013 * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053014 */
15
Kishon Vijay Abraham I3f52e1b2015-02-23 18:40:07 +053016#include <common.h>
17#include <malloc.h>
18#include <asm/io.h>
Mugunthan V N0ad3f772018-05-18 13:10:27 +020019#include <dm.h>
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +053020#include <dwc3-omap-uboot.h>
Simon Glass336d4612020-02-03 07:36:16 -070021#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070022#include <dm/devres.h>
Kishon Vijay Abraham I3f52e1b2015-02-23 18:40:07 +053023#include <linux/usb/dwc3-omap.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053024#include <linux/ioport.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053025
26#include <linux/usb/otg.h>
Kishon Vijay Abraham I3f52e1b2015-02-23 18:40:07 +053027#include <linux/compat.h>
28
29#include "linux-compat.h"
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053030
31/*
32 * All these registers belong to OMAP's Wrapper around the
33 * DesignWare USB3 Core.
34 */
35
36#define USBOTGSS_REVISION 0x0000
37#define USBOTGSS_SYSCONFIG 0x0010
38#define USBOTGSS_IRQ_EOI 0x0020
39#define USBOTGSS_EOI_OFFSET 0x0008
40#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
41#define USBOTGSS_IRQSTATUS_0 0x0028
42#define USBOTGSS_IRQENABLE_SET_0 0x002c
43#define USBOTGSS_IRQENABLE_CLR_0 0x0030
44#define USBOTGSS_IRQ0_OFFSET 0x0004
45#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
46#define USBOTGSS_IRQSTATUS_1 0x0034
47#define USBOTGSS_IRQENABLE_SET_1 0x0038
48#define USBOTGSS_IRQENABLE_CLR_1 0x003c
49#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
50#define USBOTGSS_IRQSTATUS_2 0x0044
51#define USBOTGSS_IRQENABLE_SET_2 0x0048
52#define USBOTGSS_IRQENABLE_CLR_2 0x004c
53#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
54#define USBOTGSS_IRQSTATUS_3 0x0054
55#define USBOTGSS_IRQENABLE_SET_3 0x0058
56#define USBOTGSS_IRQENABLE_CLR_3 0x005c
57#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
58#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
59#define USBOTGSS_IRQSTATUS_MISC 0x0038
60#define USBOTGSS_IRQENABLE_SET_MISC 0x003c
61#define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
62#define USBOTGSS_IRQMISC_OFFSET 0x03fc
63#define USBOTGSS_UTMI_OTG_CTRL 0x0080
64#define USBOTGSS_UTMI_OTG_STATUS 0x0084
65#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
66#define USBOTGSS_TXFIFO_DEPTH 0x0508
67#define USBOTGSS_RXFIFO_DEPTH 0x050c
68#define USBOTGSS_MMRAM_OFFSET 0x0100
69#define USBOTGSS_FLADJ 0x0104
70#define USBOTGSS_DEBUG_CFG 0x0108
71#define USBOTGSS_DEBUG_DATA 0x010c
72#define USBOTGSS_DEV_EBC_EN 0x0110
73#define USBOTGSS_DEBUG_OFFSET 0x0600
74
75/* SYSCONFIG REGISTER */
76#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
77
78/* IRQ_EOI REGISTER */
79#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
80
81/* IRQS0 BITS */
82#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
83
84/* IRQMISC BITS */
85#define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
86#define USBOTGSS_IRQMISC_OEVT (1 << 16)
87#define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
88#define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
89#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
90#define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
91#define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
92#define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
93#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
94#define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
95
Kishon Vijay Abraham I8af1be72015-08-10 16:52:54 +053096#define USBOTGSS_INTERRUPTS (USBOTGSS_IRQMISC_OEVT | \
97 USBOTGSS_IRQMISC_DRVVBUS_RISE | \
98 USBOTGSS_IRQMISC_CHRGVBUS_RISE | \
99 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | \
100 USBOTGSS_IRQMISC_IDPULLUP_RISE | \
101 USBOTGSS_IRQMISC_DRVVBUS_FALL | \
102 USBOTGSS_IRQMISC_CHRGVBUS_FALL | \
103 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | \
104 USBOTGSS_IRQMISC_IDPULLUP_FALL)
105
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530106/* UTMI_OTG_CTRL REGISTER */
107#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
108#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
109#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
110#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
111
112/* UTMI_OTG_STATUS REGISTER */
113#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
114#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
115#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
116#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
117#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
118#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
119#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
120
121struct dwc3_omap {
Marek Vasut2caf9742023-09-01 11:50:03 +0200122 struct udevice *dev;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530123
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530124 void __iomem *base;
125
126 u32 utmi_otg_status;
127 u32 utmi_otg_offset;
128 u32 irqmisc_offset;
129 u32 irq_eoi_offset;
130 u32 debug_offset;
131 u32 irq0_offset;
132
133 u32 dma_status:1;
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530134 struct list_head list;
135 u32 index;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530136};
137
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530138static LIST_HEAD(dwc3_omap_list);
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530139
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530140static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
141{
142 return readl(base + offset);
143}
144
145static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
146{
147 writel(value, base + offset);
148}
149
150static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
151{
152 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
153 omap->utmi_otg_offset);
154}
155
156static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
157{
158 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
159 omap->utmi_otg_offset, value);
160
161}
162
163static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
164{
165 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
166 omap->irq0_offset);
167}
168
169static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
170{
171 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
172 omap->irq0_offset, value);
173
174}
175
176static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
177{
178 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
179 omap->irqmisc_offset);
180}
181
182static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
183{
184 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
185 omap->irqmisc_offset, value);
186
187}
188
189static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
190{
191 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
192 omap->irqmisc_offset, value);
193
194}
195
196static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
197{
198 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
199 omap->irq0_offset, value);
200}
201
Kishon Vijay Abraham I8af1be72015-08-10 16:52:54 +0530202static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
203{
204 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
205 omap->irqmisc_offset, value);
206}
207
208static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
209{
210 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
211 omap->irq0_offset, value);
212}
213
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530214static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
215 enum omap_dwc3_vbus_id_status status)
216{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530217 u32 val;
218
219 switch (status) {
220 case OMAP_DWC3_ID_GROUND:
221 dev_dbg(omap->dev, "ID GND\n");
222
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530223 val = dwc3_omap_read_utmi_status(omap);
224 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
225 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
226 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
227 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
228 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
229 dwc3_omap_write_utmi_status(omap, val);
230 break;
231
232 case OMAP_DWC3_VBUS_VALID:
233 dev_dbg(omap->dev, "VBUS Connect\n");
234
235 val = dwc3_omap_read_utmi_status(omap);
236 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
237 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
238 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
239 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
240 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
241 dwc3_omap_write_utmi_status(omap, val);
242 break;
243
244 case OMAP_DWC3_ID_FLOAT:
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530245 case OMAP_DWC3_VBUS_OFF:
246 dev_dbg(omap->dev, "VBUS Disconnect\n");
247
248 val = dwc3_omap_read_utmi_status(omap);
249 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
250 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
251 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
252 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
253 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
254 dwc3_omap_write_utmi_status(omap, val);
255 break;
256
257 default:
258 dev_dbg(omap->dev, "invalid state\n");
259 }
260}
261
262static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
263{
264 struct dwc3_omap *omap = _omap;
265 u32 reg;
266
267 reg = dwc3_omap_read_irqmisc_status(omap);
268
269 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
270 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
271 omap->dma_status = false;
272 }
273
274 if (reg & USBOTGSS_IRQMISC_OEVT)
275 dev_dbg(omap->dev, "OTG Event\n");
276
277 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
278 dev_dbg(omap->dev, "DRVVBUS Rise\n");
279
280 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
281 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
282
283 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
284 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
285
286 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
287 dev_dbg(omap->dev, "IDPULLUP Rise\n");
288
289 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
290 dev_dbg(omap->dev, "DRVVBUS Fall\n");
291
292 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
293 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
294
295 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
296 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
297
298 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
299 dev_dbg(omap->dev, "IDPULLUP Fall\n");
300
301 dwc3_omap_write_irqmisc_status(omap, reg);
302
303 reg = dwc3_omap_read_irq0_status(omap);
304
305 dwc3_omap_write_irq0_status(omap, reg);
306
307 return IRQ_HANDLED;
308}
309
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530310static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
311{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530312 /* enable all IRQs */
Kishon Vijay Abraham I8af1be72015-08-10 16:52:54 +0530313 dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530314
Kishon Vijay Abraham I8af1be72015-08-10 16:52:54 +0530315 dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530316}
317
318static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
319{
320 /* disable all IRQs */
Kishon Vijay Abraham I8af1be72015-08-10 16:52:54 +0530321 dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST);
322
323 dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530324}
325
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530326static void dwc3_omap_map_offset(struct dwc3_omap *omap)
327{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530328 /*
329 * Differentiate between OMAP5 and AM437x.
330 *
331 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
332 * though there are changes in wrapper register offsets.
333 *
334 * Using dt compatible to differentiate AM437x.
335 */
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530336#ifdef CONFIG_AM43XX
337 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
338 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
339 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
340 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
341 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
342#endif
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530343}
344
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530345static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode)
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530346{
347 u32 reg;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530348
349 reg = dwc3_omap_read_utmi_status(omap);
350
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530351 switch (utmi_mode) {
352 case DWC3_OMAP_UTMI_MODE_SW:
353 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
354 break;
355 case DWC3_OMAP_UTMI_MODE_HW:
356 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
357 break;
358 default:
359 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
360 }
361
362 dwc3_omap_write_utmi_status(omap, reg);
363}
364
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530365/**
366 * dwc3_omap_uboot_init - dwc3 omap uboot initialization code
367 * @dev: struct dwc3_omap_device containing initialization data
368 *
369 * Entry point for dwc3 omap driver (equivalent to dwc3_omap_probe in linux
370 * kernel driver). Pointer to dwc3_omap_device should be passed containing
371 * base address and other initialization data. Returns '0' on success and
372 * a negative value on failure.
373 *
374 * Generally called from board_usb_init() implemented in board file.
375 */
376int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev)
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530377{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530378 u32 reg;
Felipe Balbic2ad4e12015-10-01 14:22:18 -0500379 struct device *dev = NULL;
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530380 struct dwc3_omap *omap;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530381
Mugunthan V N0ad3f772018-05-18 13:10:27 +0200382 omap = devm_kzalloc((struct udevice *)dev, sizeof(*omap), GFP_KERNEL);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530383 if (!omap)
384 return -ENOMEM;
385
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530386 omap->base = omap_dev->base;
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530387 omap->index = omap_dev->index;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530388
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530389 dwc3_omap_map_offset(omap);
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530390 dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530391
392 /* check the DMA Status */
393 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
394 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
395
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530396 dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status);
397
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530398 dwc3_omap_enable_irqs(omap);
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530399 list_add_tail(&omap->list, &dwc3_omap_list);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530400
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530401 return 0;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530402}
403
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530404/**
405 * dwc3_omap_uboot_exit - dwc3 omap uboot cleanup code
406 * @index: index of this controller
407 *
408 * Performs cleanup of memory allocated in dwc3_omap_uboot_init
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530409 * (equivalent to dwc3_omap_remove in linux). index of _this_ controller
410 * should be passed and should match with the index passed in
411 * dwc3_omap_device during init.
Kishon Vijay Abraham Ic241d7e2015-02-23 18:40:09 +0530412 *
413 * Generally called from board file.
414 */
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530415void dwc3_omap_uboot_exit(int index)
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530416{
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530417 struct dwc3_omap *omap = NULL;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530418
Kishon Vijay Abraham I57207652015-02-23 18:40:10 +0530419 list_for_each_entry(omap, &dwc3_omap_list, list) {
420 if (omap->index != index)
421 continue;
422
423 dwc3_omap_disable_irqs(omap);
424 list_del(&omap->list);
425 kfree(omap);
426 break;
427 }
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530428}
429
Kishon Vijay Abraham I53de33f2015-02-23 18:40:11 +0530430/**
431 * dwc3_omap_uboot_interrupt_status - check the status of interrupt
Marek Vasut2caf9742023-09-01 11:50:03 +0200432 * @dev: device of this controller
Kishon Vijay Abraham I53de33f2015-02-23 18:40:11 +0530433 *
434 * Checks the status of interrupts and returns true if an interrupt
435 * is detected or false otherwise.
436 *
437 * Generally called from board file.
438 */
Marek Vasut2caf9742023-09-01 11:50:03 +0200439int dwc3_omap_uboot_interrupt_status(struct udevice *dev)
Kishon Vijay Abraham I53de33f2015-02-23 18:40:11 +0530440{
441 struct dwc3_omap *omap = NULL;
442
443 list_for_each_entry(omap, &dwc3_omap_list, list)
Marek Vasut2caf9742023-09-01 11:50:03 +0200444 if (omap->dev == dev)
Kishon Vijay Abraham I53de33f2015-02-23 18:40:11 +0530445 return dwc3_omap_interrupt(-1, omap);
446
447 return 0;
448}
449
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530450MODULE_ALIAS("platform:omap-dwc3");
451MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
452MODULE_LICENSE("GPL v2");
453MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");