blob: 68cf32cd189c44d49b058851a45b48b1fa6e9531 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302/**
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +05305 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05306 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +053010 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
11 * to uboot.
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053012 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +053013 * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053014 */
15
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +053016#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070017#include <cpu_func.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060018#include <log.h>
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +053019#include <malloc.h>
Sean Andersondf5eabc2020-09-15 10:45:16 -040020#include <dm.h>
Simon Glass336d4612020-02-03 07:36:16 -070021#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070022#include <dm/devres.h>
Masahiro Yamada84b8bf62016-01-24 23:27:48 +090023#include <linux/bug.h>
Simon Glassc05ed002020-05-10 11:40:11 -060024#include <linux/delay.h>
Masahiro Yamada9d86b892020-02-14 16:40:19 +090025#include <linux/dma-mapping.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053026#include <linux/list.h>
Simon Glass1e94b462023-09-14 18:21:46 -060027#include <linux/printk.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053028
29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
31
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053032#include "core.h"
33#include "gadget.h"
34#include "io.h"
35
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +053036#include "linux-compat.h"
37
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053038/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
97 int retries = 10000;
98 u32 reg;
99
100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
131 /* wait for a change in DSTS */
132 retries = 10000;
133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
139 udelay(5);
140 }
141
142 dev_vdbg(dwc->dev, "link state change request timed out\n");
143
144 return -ETIMEDOUT;
145}
146
147/**
148 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
149 * @dwc: pointer to our context structure
150 *
151 * This function will a best effort FIFO allocation in order
152 * to improve FIFO usage and throughput, while still allowing
153 * us to enable as many endpoints as possible.
154 *
155 * Keep in mind that this operation will be highly dependent
156 * on the configured size for RAM1 - which contains TxFifo -,
157 * the amount of endpoints enabled on coreConsultant tool, and
158 * the width of the Master Bus.
159 *
160 * In the ideal world, we would always be able to satisfy the
161 * following equation:
162 *
163 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
164 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
165 *
166 * Unfortunately, due to many variables that's not always the case.
167 */
168int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
169{
170 int last_fifo_depth = 0;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530171 int fifo_size;
172 int mdwidth;
173 int num;
174
175 if (!dwc->needs_fifo_resize)
176 return 0;
177
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530178 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
179
180 /* MDWIDTH is represented in bits, we need it in bytes */
181 mdwidth >>= 3;
182
183 /*
184 * FIXME For now we will only allocate 1 wMaxPacketSize space
185 * for each enabled endpoint, later patches will come to
186 * improve this algorithm so that we better use the internal
187 * FIFO space
188 */
189 for (num = 0; num < dwc->num_in_eps; num++) {
190 /* bit0 indicates direction; 1 means IN ep */
191 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
192 int mult = 1;
193 int tmp;
194
195 if (!(dep->flags & DWC3_EP_ENABLED))
196 continue;
197
198 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
199 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
200 mult = 3;
201
202 /*
203 * REVISIT: the following assumes we will always have enough
204 * space available on the FIFO RAM for all possible use cases.
205 * Make sure that's true somehow and change FIFO allocation
206 * accordingly.
207 *
208 * If we have Bulk or Isochronous endpoints, we want
209 * them to be able to be very, very fast. So we're giving
210 * those endpoints a fifo_size which is enough for 3 full
211 * packets
212 */
213 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
214 tmp += mdwidth;
215
216 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
217
218 fifo_size |= (last_fifo_depth << 16);
219
220 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
221 dep->name, last_fifo_depth, fifo_size & 0xffff);
222
223 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
224
225 last_fifo_depth += (fifo_size & 0xffff);
226 }
227
228 return 0;
229}
230
231void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
232 int status)
233{
234 struct dwc3 *dwc = dep->dwc;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530235
236 if (req->queued) {
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +0530237 dep->busy_slot++;
238 /*
239 * Skip LINK TRB. We can't use req->trb and check for
240 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
241 * just completed (not the LINK TRB).
242 */
243 if (((dep->busy_slot & DWC3_TRB_MASK) ==
244 DWC3_TRB_NUM- 1) &&
245 usb_endpoint_xfer_isoc(dep->endpoint.desc))
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530246 dep->busy_slot++;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530247 req->queued = false;
248 }
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +0530249
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530250 list_del(&req->list);
251 req->trb = NULL;
Marek Szyprowskifd15b582019-10-02 14:19:14 +0200252 if (req->request.length)
253 dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530254
255 if (req->request.status == -EINPROGRESS)
256 req->request.status = status;
257
258 if (dwc->ep0_bounced && dep->number == 0)
259 dwc->ep0_bounced = false;
260 else
261 usb_gadget_unmap_request(&dwc->gadget, &req->request,
262 req->direction);
263
264 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
265 req, dep->name, req->request.actual,
266 req->request.length, status);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530267
268 spin_unlock(&dwc->lock);
269 usb_gadget_giveback_request(&dep->endpoint, &req->request);
270 spin_lock(&dwc->lock);
271}
272
273int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
274{
275 u32 timeout = 500;
276 u32 reg;
277
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530278 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
279 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
280
281 do {
282 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
283 if (!(reg & DWC3_DGCMD_CMDACT)) {
284 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
285 DWC3_DGCMD_STATUS(reg));
286 return 0;
287 }
288
289 /*
290 * We can't sleep here, because it's also called from
291 * interrupt context.
292 */
293 timeout--;
294 if (!timeout)
295 return -ETIMEDOUT;
296 udelay(1);
297 } while (1);
298}
299
300int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
301 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
302{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530303 u32 timeout = 500;
304 u32 reg;
305
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530306 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
307 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
308 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
309
310 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
311 do {
312 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
313 if (!(reg & DWC3_DEPCMD_CMDACT)) {
314 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
315 DWC3_DEPCMD_STATUS(reg));
316 return 0;
317 }
318
319 /*
320 * We can't sleep here, because it is also called from
321 * interrupt context.
322 */
323 timeout--;
324 if (!timeout)
325 return -ETIMEDOUT;
326
327 udelay(1);
328 } while (1);
329}
330
331static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
332 struct dwc3_trb *trb)
333{
334 u32 offset = (char *) trb - (char *) dep->trb_pool;
335
336 return dep->trb_pool_dma + offset;
337}
338
339static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
340{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530341 if (dep->trb_pool)
342 return 0;
343
344 if (dep->number == 0 || dep->number == 1)
345 return 0;
346
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +0530347 dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
348 DWC3_TRB_NUM,
349 (unsigned long *)&dep->trb_pool_dma);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530350 if (!dep->trb_pool) {
351 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
352 dep->name);
353 return -ENOMEM;
354 }
355
356 return 0;
357}
358
359static void dwc3_free_trb_pool(struct dwc3_ep *dep)
360{
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +0530361 dma_free_coherent(dep->trb_pool);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530362
363 dep->trb_pool = NULL;
364 dep->trb_pool_dma = 0;
365}
366
367static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
368{
369 struct dwc3_gadget_ep_cmd_params params;
370 u32 cmd;
371
372 memset(&params, 0x00, sizeof(params));
373
374 if (dep->number != 1) {
375 cmd = DWC3_DEPCMD_DEPSTARTCFG;
376 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
377 if (dep->number > 1) {
378 if (dwc->start_config_issued)
379 return 0;
380 dwc->start_config_issued = true;
381 cmd |= DWC3_DEPCMD_PARAM(2);
382 }
383
384 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
385 }
386
387 return 0;
388}
389
390static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
391 const struct usb_endpoint_descriptor *desc,
392 const struct usb_ss_ep_comp_descriptor *comp_desc,
393 bool ignore, bool restore)
394{
395 struct dwc3_gadget_ep_cmd_params params;
396
397 memset(&params, 0x00, sizeof(params));
398
399 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
400 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
401
402 /* Burst size is only needed in SuperSpeed mode */
403 if (dwc->gadget.speed == USB_SPEED_SUPER) {
404 u32 burst = dep->endpoint.maxburst - 1;
405
406 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
407 }
408
409 if (ignore)
410 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
411
412 if (restore) {
413 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
414 params.param2 |= dep->saved_state;
415 }
416
417 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
418 | DWC3_DEPCFG_XFER_NOT_READY_EN;
419
420 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
421 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
422 | DWC3_DEPCFG_STREAM_EVENT_EN;
423 dep->stream_capable = true;
424 }
425
426 if (!usb_endpoint_xfer_control(desc))
427 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
428
429 /*
430 * We are doing 1:1 mapping for endpoints, meaning
431 * Physical Endpoints 2 maps to Logical Endpoint 2 and
432 * so on. We consider the direction bit as part of the physical
433 * endpoint number. So USB endpoint 0x81 is 0x03.
434 */
435 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
436
437 /*
438 * We must use the lower 16 TX FIFOs even though
439 * HW might have more
440 */
441 if (dep->direction)
442 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
443
444 if (desc->bInterval) {
445 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
446 dep->interval = 1 << (desc->bInterval - 1);
447 }
448
449 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
450 DWC3_DEPCMD_SETEPCONFIG, &params);
451}
452
453static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
454{
455 struct dwc3_gadget_ep_cmd_params params;
456
457 memset(&params, 0x00, sizeof(params));
458
459 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
460
461 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
462 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
463}
464
465/**
466 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
467 * @dep: endpoint to be initialized
468 * @desc: USB Endpoint Descriptor
469 *
470 * Caller should take care of locking
471 */
472static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
473 const struct usb_endpoint_descriptor *desc,
474 const struct usb_ss_ep_comp_descriptor *comp_desc,
475 bool ignore, bool restore)
476{
477 struct dwc3 *dwc = dep->dwc;
478 u32 reg;
479 int ret;
480
481 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
482
483 if (!(dep->flags & DWC3_EP_ENABLED)) {
484 ret = dwc3_gadget_start_config(dwc, dep);
485 if (ret)
486 return ret;
487 }
488
489 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
490 restore);
491 if (ret)
492 return ret;
493
494 if (!(dep->flags & DWC3_EP_ENABLED)) {
495 struct dwc3_trb *trb_st_hw;
496 struct dwc3_trb *trb_link;
497
498 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
499 if (ret)
500 return ret;
501
502 dep->endpoint.desc = desc;
503 dep->comp_desc = comp_desc;
504 dep->type = usb_endpoint_type(desc);
505 dep->flags |= DWC3_EP_ENABLED;
506
507 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
508 reg |= DWC3_DALEPENA_EP(dep->number);
509 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
510
511 if (!usb_endpoint_xfer_isoc(desc))
512 return 0;
513
514 /* Link TRB for ISOC. The HWO bit is never reset */
515 trb_st_hw = &dep->trb_pool[0];
516
517 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
518 memset(trb_link, 0, sizeof(*trb_link));
519
520 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
521 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
522 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
523 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
524 }
525
526 return 0;
527}
528
529static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
530static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
531{
532 struct dwc3_request *req;
533
534 if (!list_empty(&dep->req_queued)) {
535 dwc3_stop_active_transfer(dwc, dep->number, true);
536
537 /* - giveback all requests to gadget driver */
538 while (!list_empty(&dep->req_queued)) {
539 req = next_request(&dep->req_queued);
540
541 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
542 }
543 }
544
545 while (!list_empty(&dep->request_list)) {
546 req = next_request(&dep->request_list);
547
548 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
549 }
550}
551
552/**
553 * __dwc3_gadget_ep_disable - Disables a HW endpoint
554 * @dep: the endpoint to disable
555 *
556 * This function also removes requests which are currently processed ny the
557 * hardware and those which are not yet scheduled.
558 * Caller should take care of locking.
559 */
560static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
561{
562 struct dwc3 *dwc = dep->dwc;
563 u32 reg;
564
565 dwc3_remove_requests(dwc, dep);
566
567 /* make sure HW endpoint isn't stalled */
568 if (dep->flags & DWC3_EP_STALL)
569 __dwc3_gadget_ep_set_halt(dep, 0, false);
570
571 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
572 reg &= ~DWC3_DALEPENA_EP(dep->number);
573 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
574
575 dep->stream_capable = false;
576 dep->endpoint.desc = NULL;
577 dep->comp_desc = NULL;
578 dep->type = 0;
579 dep->flags = 0;
580
581 return 0;
582}
583
584/* -------------------------------------------------------------------------- */
585
586static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
587 const struct usb_endpoint_descriptor *desc)
588{
589 return -EINVAL;
590}
591
592static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
593{
594 return -EINVAL;
595}
596
597/* -------------------------------------------------------------------------- */
598
599static int dwc3_gadget_ep_enable(struct usb_ep *ep,
600 const struct usb_endpoint_descriptor *desc)
601{
602 struct dwc3_ep *dep;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530603 unsigned long flags;
604 int ret;
605
606 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
607 pr_debug("dwc3: invalid parameters\n");
608 return -EINVAL;
609 }
610
611 if (!desc->wMaxPacketSize) {
612 pr_debug("dwc3: missing wMaxPacketSize\n");
613 return -EINVAL;
614 }
615
616 dep = to_dwc3_ep(ep);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530617
618 if (dep->flags & DWC3_EP_ENABLED) {
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +0530619 WARN(true, "%s is already enabled\n",
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530620 dep->name);
621 return 0;
622 }
623
624 switch (usb_endpoint_type(desc)) {
625 case USB_ENDPOINT_XFER_CONTROL:
626 strlcat(dep->name, "-control", sizeof(dep->name));
627 break;
628 case USB_ENDPOINT_XFER_ISOC:
629 strlcat(dep->name, "-isoc", sizeof(dep->name));
630 break;
631 case USB_ENDPOINT_XFER_BULK:
632 strlcat(dep->name, "-bulk", sizeof(dep->name));
633 break;
634 case USB_ENDPOINT_XFER_INT:
635 strlcat(dep->name, "-int", sizeof(dep->name));
636 break;
637 default:
Sean Andersondf5eabc2020-09-15 10:45:16 -0400638 dev_err(dep->dwc->dev, "invalid endpoint transfer type\n");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530639 }
640
641 spin_lock_irqsave(&dwc->lock, flags);
642 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
643 spin_unlock_irqrestore(&dwc->lock, flags);
644
645 return ret;
646}
647
648static int dwc3_gadget_ep_disable(struct usb_ep *ep)
649{
650 struct dwc3_ep *dep;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530651 unsigned long flags;
652 int ret;
653
654 if (!ep) {
655 pr_debug("dwc3: invalid parameters\n");
656 return -EINVAL;
657 }
658
659 dep = to_dwc3_ep(ep);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530660
661 if (!(dep->flags & DWC3_EP_ENABLED)) {
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +0530662 WARN(true, "%s is already disabled\n",
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530663 dep->name);
664 return 0;
665 }
666
667 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
668 dep->number >> 1,
669 (dep->number & 1) ? "in" : "out");
670
671 spin_lock_irqsave(&dwc->lock, flags);
672 ret = __dwc3_gadget_ep_disable(dep);
673 spin_unlock_irqrestore(&dwc->lock, flags);
674
675 return ret;
676}
677
678static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
679 gfp_t gfp_flags)
680{
681 struct dwc3_request *req;
682 struct dwc3_ep *dep = to_dwc3_ep(ep);
683
684 req = kzalloc(sizeof(*req), gfp_flags);
685 if (!req)
686 return NULL;
687
688 req->epnum = dep->number;
689 req->dep = dep;
690
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530691 return &req->request;
692}
693
694static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
695 struct usb_request *request)
696{
697 struct dwc3_request *req = to_dwc3_request(request);
698
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530699 kfree(req);
700}
701
702/**
703 * dwc3_prepare_one_trb - setup one TRB from one request
704 * @dep: endpoint for which this request is prepared
705 * @req: dwc3_request pointer
706 */
707static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
708 struct dwc3_request *req, dma_addr_t dma,
709 unsigned length, unsigned last, unsigned chain, unsigned node)
710{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530711 struct dwc3_trb *trb;
712
Sean Andersondf5eabc2020-09-15 10:45:16 -0400713 dev_vdbg(dep->dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
714 dep->name, req, (unsigned long long)dma,
715 length, last ? " last" : "", chain ? " chain" : "");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530716
717
718 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
719
720 if (!req->trb) {
721 dwc3_gadget_move_request_queued(req);
722 req->trb = trb;
723 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
724 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
725 }
726
727 dep->free_slot++;
728 /* Skip the LINK-TRB on ISOC */
729 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
730 usb_endpoint_xfer_isoc(dep->endpoint.desc))
731 dep->free_slot++;
732
733 trb->size = DWC3_TRB_SIZE_LENGTH(length);
734 trb->bpl = lower_32_bits(dma);
735 trb->bph = upper_32_bits(dma);
736
737 switch (usb_endpoint_type(dep->endpoint.desc)) {
738 case USB_ENDPOINT_XFER_CONTROL:
739 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
740 break;
741
742 case USB_ENDPOINT_XFER_ISOC:
743 if (!node)
744 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
745 else
746 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
747 break;
748
749 case USB_ENDPOINT_XFER_BULK:
750 case USB_ENDPOINT_XFER_INT:
751 trb->ctrl = DWC3_TRBCTL_NORMAL;
752 break;
753 default:
754 /*
755 * This is only possible with faulty memory because we
756 * checked it already :)
757 */
758 BUG();
759 }
760
761 if (!req->request.no_interrupt && !chain)
762 trb->ctrl |= DWC3_TRB_CTRL_IOC;
763
764 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
765 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
766 trb->ctrl |= DWC3_TRB_CTRL_CSP;
767 } else if (last) {
768 trb->ctrl |= DWC3_TRB_CTRL_LST;
769 }
770
771 if (chain)
772 trb->ctrl |= DWC3_TRB_CTRL_CHN;
773
774 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
775 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
776
777 trb->ctrl |= DWC3_TRB_CTRL_HWO;
Kishon Vijay Abraham I526a50f2015-02-23 18:40:13 +0530778
Philipp Tomsichb7bf4a92017-04-06 16:58:52 +0200779 dwc3_flush_cache((uintptr_t)dma, length);
780 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530781}
782
783/*
784 * dwc3_prepare_trbs - setup TRBs from requests
785 * @dep: endpoint for which requests are being prepared
786 * @starting: true if the endpoint is idle and no requests are queued.
787 *
788 * The function goes through the requests list and sets up TRBs for the
789 * transfers. The function returns once there are no more TRBs available or
790 * it runs out of requests.
791 */
792static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
793{
794 struct dwc3_request *req, *n;
795 u32 trbs_left;
796 u32 max;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530797
798 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
799
800 /* the first request must not be queued */
801 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
802
803 /* Can't wrap around on a non-isoc EP since there's no link TRB */
804 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
805 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
806 if (trbs_left > max)
807 trbs_left = max;
808 }
809
810 /*
811 * If busy & slot are equal than it is either full or empty. If we are
812 * starting to process requests then we are empty. Otherwise we are
813 * full and don't do anything
814 */
815 if (!trbs_left) {
816 if (!starting)
817 return;
818 trbs_left = DWC3_TRB_NUM;
819 /*
820 * In case we start from scratch, we queue the ISOC requests
821 * starting from slot 1. This is done because we use ring
822 * buffer and have no LST bit to stop us. Instead, we place
823 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
824 * after the first request so we start at slot 1 and have
825 * 7 requests proceed before we hit the first IOC.
826 * Other transfer types don't use the ring buffer and are
827 * processed from the first TRB until the last one. Since we
828 * don't wrap around we have to start at the beginning.
829 */
830 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
831 dep->busy_slot = 1;
832 dep->free_slot = 1;
833 } else {
834 dep->busy_slot = 0;
835 dep->free_slot = 0;
836 }
837 }
838
839 /* The last TRB is a link TRB, not used for xfer */
840 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
841 return;
842
843 list_for_each_entry_safe(req, n, &dep->request_list, list) {
844 unsigned length;
845 dma_addr_t dma;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530846
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +0530847 dma = req->request.dma;
848 length = req->request.length;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530849
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +0530850 dwc3_prepare_one_trb(dep, req, dma, length,
Lukasz Majewski29e7fc12015-03-03 17:32:13 +0100851 true, false, 0);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530852
Lukasz Majewski29e7fc12015-03-03 17:32:13 +0100853 break;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530854 }
855}
856
857static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
858 int start_new)
859{
860 struct dwc3_gadget_ep_cmd_params params;
861 struct dwc3_request *req;
862 struct dwc3 *dwc = dep->dwc;
863 int ret;
864 u32 cmd;
865
866 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
867 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
868 return -EBUSY;
869 }
870 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
871
872 /*
873 * If we are getting here after a short-out-packet we don't enqueue any
874 * new requests as we try to set the IOC bit only on the last request.
875 */
876 if (start_new) {
877 if (list_empty(&dep->req_queued))
878 dwc3_prepare_trbs(dep, start_new);
879
880 /* req points to the first request which will be sent */
881 req = next_request(&dep->req_queued);
882 } else {
883 dwc3_prepare_trbs(dep, start_new);
884
885 /*
886 * req points to the first request where HWO changed from 0 to 1
887 */
888 req = next_request(&dep->req_queued);
889 }
890 if (!req) {
891 dep->flags |= DWC3_EP_PENDING_REQUEST;
892 return 0;
893 }
894
895 memset(&params, 0, sizeof(params));
896
897 if (start_new) {
898 params.param0 = upper_32_bits(req->trb_dma);
899 params.param1 = lower_32_bits(req->trb_dma);
900 cmd = DWC3_DEPCMD_STARTTRANSFER;
901 } else {
902 cmd = DWC3_DEPCMD_UPDATETRANSFER;
903 }
904
905 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
906 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
907 if (ret < 0) {
908 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
909
910 /*
911 * FIXME we need to iterate over the list of requests
912 * here and stop, unmap, free and del each of the linked
913 * requests instead of what we do now.
914 */
915 usb_gadget_unmap_request(&dwc->gadget, &req->request,
916 req->direction);
917 list_del(&req->list);
918 return ret;
919 }
920
921 dep->flags |= DWC3_EP_BUSY;
922
923 if (start_new) {
924 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
925 dep->number);
926 WARN_ON_ONCE(!dep->resource_index);
927 }
928
929 return 0;
930}
931
932static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
933 struct dwc3_ep *dep, u32 cur_uf)
934{
935 u32 uf;
936
937 if (list_empty(&dep->request_list)) {
938 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
939 dep->name);
940 dep->flags |= DWC3_EP_PENDING_REQUEST;
941 return;
942 }
943
944 /* 4 micro frames in the future */
945 uf = cur_uf + dep->interval * 4;
946
947 __dwc3_gadget_kick_transfer(dep, uf, 1);
948}
949
950static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
951 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
952{
953 u32 cur_uf, mask;
954
955 mask = ~(dep->interval - 1);
956 cur_uf = event->parameters & mask;
957
958 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
959}
960
961static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
962{
963 struct dwc3 *dwc = dep->dwc;
964 int ret;
965
966 req->request.actual = 0;
967 req->request.status = -EINPROGRESS;
968 req->direction = dep->direction;
969 req->epnum = dep->number;
970
971 /*
Marek Szyprowski5dc45382015-03-03 17:32:10 +0100972 * DWC3 hangs on OUT requests smaller than maxpacket size,
973 * so HACK the request length
974 */
975 if (dep->direction == 0 &&
976 req->request.length < dep->endpoint.maxpacket)
977 req->request.length = dep->endpoint.maxpacket;
978
979 /*
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530980 * We only add to our list of requests now and
981 * start consuming the list once we get XferNotReady
982 * IRQ.
983 *
984 * That way, we avoid doing anything that we don't need
985 * to do now and defer it until the point we receive a
986 * particular token from the Host side.
987 *
988 * This will also avoid Host cancelling URBs due to too
989 * many NAKs.
990 */
991 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
992 dep->direction);
993 if (ret)
994 return ret;
995
996 list_add_tail(&req->list, &dep->request_list);
997
998 /*
999 * There are a few special cases:
1000 *
1001 * 1. XferNotReady with empty list of requests. We need to kick the
1002 * transfer here in that situation, otherwise we will be NAKing
1003 * forever. If we get XferNotReady before gadget driver has a
1004 * chance to queue a request, we will ACK the IRQ but won't be
1005 * able to receive the data until the next request is queued.
1006 * The following code is handling exactly that.
1007 *
1008 */
1009 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1010 /*
1011 * If xfernotready is already elapsed and it is a case
1012 * of isoc transfer, then issue END TRANSFER, so that
1013 * you can receive xfernotready again and can have
1014 * notion of current microframe.
1015 */
1016 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1017 if (list_empty(&dep->req_queued)) {
1018 dwc3_stop_active_transfer(dwc, dep->number, true);
1019 dep->flags = DWC3_EP_ENABLED;
1020 }
1021 return 0;
1022 }
1023
1024 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1025 if (ret && ret != -EBUSY)
1026 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1027 dep->name);
1028 return ret;
1029 }
1030
1031 /*
1032 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1033 * kick the transfer here after queuing a request, otherwise the
1034 * core may not see the modified TRB(s).
1035 */
1036 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1037 (dep->flags & DWC3_EP_BUSY) &&
1038 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1039 WARN_ON_ONCE(!dep->resource_index);
1040 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1041 false);
1042 if (ret && ret != -EBUSY)
1043 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1044 dep->name);
1045 return ret;
1046 }
1047
1048 /*
1049 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1050 * right away, otherwise host will not know we have streams to be
1051 * handled.
1052 */
1053 if (dep->stream_capable) {
1054 int ret;
1055
1056 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1057 if (ret && ret != -EBUSY) {
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301058 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1059 dep->name);
1060 }
1061 }
1062
1063 return 0;
1064}
1065
1066static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1067 gfp_t gfp_flags)
1068{
1069 struct dwc3_request *req = to_dwc3_request(request);
1070 struct dwc3_ep *dep = to_dwc3_ep(ep);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301071
1072 unsigned long flags;
1073
1074 int ret;
1075
1076 spin_lock_irqsave(&dwc->lock, flags);
1077 if (!dep->endpoint.desc) {
Sean Andersondf5eabc2020-09-15 10:45:16 -04001078 dev_dbg(dep->dwc->dev,
1079 "trying to queue request %p to disabled %s\n", request,
1080 ep->name);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301081 ret = -ESHUTDOWN;
1082 goto out;
1083 }
1084
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05301085 if (req->dep != dep) {
Sean Andersondf5eabc2020-09-15 10:45:16 -04001086 WARN(true, "request %p belongs to '%s'\n", request,
1087 req->dep->name);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301088 ret = -EINVAL;
1089 goto out;
1090 }
1091
Sean Andersondf5eabc2020-09-15 10:45:16 -04001092 dev_vdbg(dep->dwc->dev, "queing request %p to %s length %d\n",
1093 request, ep->name, request->length);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301094
1095 ret = __dwc3_gadget_ep_queue(dep, req);
1096
1097out:
1098 spin_unlock_irqrestore(&dwc->lock, flags);
1099
1100 return ret;
1101}
1102
1103static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1104 struct usb_request *request)
1105{
1106 struct dwc3_request *req = to_dwc3_request(request);
1107 struct dwc3_request *r = NULL;
1108
1109 struct dwc3_ep *dep = to_dwc3_ep(ep);
1110 struct dwc3 *dwc = dep->dwc;
1111
1112 unsigned long flags;
1113 int ret = 0;
1114
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301115 spin_lock_irqsave(&dwc->lock, flags);
1116
1117 list_for_each_entry(r, &dep->request_list, list) {
1118 if (r == req)
1119 break;
1120 }
1121
1122 if (r != req) {
1123 list_for_each_entry(r, &dep->req_queued, list) {
1124 if (r == req)
1125 break;
1126 }
1127 if (r == req) {
1128 /* wait until it is processed */
1129 dwc3_stop_active_transfer(dwc, dep->number, true);
1130 goto out1;
1131 }
1132 dev_err(dwc->dev, "request %p was not queued to %s\n",
1133 request, ep->name);
1134 ret = -EINVAL;
1135 goto out0;
1136 }
1137
1138out1:
1139 /* giveback the request */
1140 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1141
1142out0:
1143 spin_unlock_irqrestore(&dwc->lock, flags);
1144
1145 return ret;
1146}
1147
1148int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1149{
1150 struct dwc3_gadget_ep_cmd_params params;
1151 struct dwc3 *dwc = dep->dwc;
1152 int ret;
1153
1154 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1155 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1156 return -EINVAL;
1157 }
1158
1159 memset(&params, 0x00, sizeof(params));
1160
1161 if (value) {
1162 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1163 (!list_empty(&dep->req_queued) ||
1164 !list_empty(&dep->request_list)))) {
1165 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1166 dep->name);
1167 return -EAGAIN;
1168 }
1169
1170 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1171 DWC3_DEPCMD_SETSTALL, &params);
1172 if (ret)
1173 dev_err(dwc->dev, "failed to set STALL on %s\n",
1174 dep->name);
1175 else
1176 dep->flags |= DWC3_EP_STALL;
1177 } else {
1178 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1179 DWC3_DEPCMD_CLEARSTALL, &params);
1180 if (ret)
1181 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1182 dep->name);
1183 else
1184 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1185 }
1186
1187 return ret;
1188}
1189
1190static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1191{
1192 struct dwc3_ep *dep = to_dwc3_ep(ep);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301193
1194 unsigned long flags;
1195
1196 int ret;
1197
1198 spin_lock_irqsave(&dwc->lock, flags);
1199 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1200 spin_unlock_irqrestore(&dwc->lock, flags);
1201
1202 return ret;
1203}
1204
1205static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1206{
1207 struct dwc3_ep *dep = to_dwc3_ep(ep);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301208 unsigned long flags;
1209 int ret;
1210
1211 spin_lock_irqsave(&dwc->lock, flags);
1212 dep->flags |= DWC3_EP_WEDGE;
1213
1214 if (dep->number == 0 || dep->number == 1)
1215 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1216 else
1217 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1218 spin_unlock_irqrestore(&dwc->lock, flags);
1219
1220 return ret;
1221}
1222
1223/* -------------------------------------------------------------------------- */
1224
1225static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1226 .bLength = USB_DT_ENDPOINT_SIZE,
1227 .bDescriptorType = USB_DT_ENDPOINT,
1228 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1229};
1230
1231static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1232 .enable = dwc3_gadget_ep0_enable,
1233 .disable = dwc3_gadget_ep0_disable,
1234 .alloc_request = dwc3_gadget_ep_alloc_request,
1235 .free_request = dwc3_gadget_ep_free_request,
1236 .queue = dwc3_gadget_ep0_queue,
1237 .dequeue = dwc3_gadget_ep_dequeue,
1238 .set_halt = dwc3_gadget_ep0_set_halt,
1239 .set_wedge = dwc3_gadget_ep_set_wedge,
1240};
1241
1242static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1243 .enable = dwc3_gadget_ep_enable,
1244 .disable = dwc3_gadget_ep_disable,
1245 .alloc_request = dwc3_gadget_ep_alloc_request,
1246 .free_request = dwc3_gadget_ep_free_request,
1247 .queue = dwc3_gadget_ep_queue,
1248 .dequeue = dwc3_gadget_ep_dequeue,
1249 .set_halt = dwc3_gadget_ep_set_halt,
1250 .set_wedge = dwc3_gadget_ep_set_wedge,
1251};
1252
1253/* -------------------------------------------------------------------------- */
1254
1255static int dwc3_gadget_get_frame(struct usb_gadget *g)
1256{
1257 struct dwc3 *dwc = gadget_to_dwc(g);
1258 u32 reg;
1259
1260 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1261 return DWC3_DSTS_SOFFN(reg);
1262}
1263
1264static int dwc3_gadget_wakeup(struct usb_gadget *g)
1265{
1266 struct dwc3 *dwc = gadget_to_dwc(g);
1267
1268 unsigned long timeout;
1269 unsigned long flags;
1270
1271 u32 reg;
1272
1273 int ret = 0;
1274
1275 u8 link_state;
1276 u8 speed;
1277
1278 spin_lock_irqsave(&dwc->lock, flags);
1279
1280 /*
1281 * According to the Databook Remote wakeup request should
1282 * be issued only when the device is in early suspend state.
1283 *
1284 * We can check that via USB Link State bits in DSTS register.
1285 */
1286 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1287
1288 speed = reg & DWC3_DSTS_CONNECTSPD;
1289 if (speed == DWC3_DSTS_SUPERSPEED) {
1290 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1291 ret = -EINVAL;
1292 goto out;
1293 }
1294
1295 link_state = DWC3_DSTS_USBLNKST(reg);
1296
1297 switch (link_state) {
1298 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1299 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1300 break;
1301 default:
1302 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1303 link_state);
1304 ret = -EINVAL;
1305 goto out;
1306 }
1307
1308 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1309 if (ret < 0) {
1310 dev_err(dwc->dev, "failed to put link in Recovery\n");
1311 goto out;
1312 }
1313
1314 /* Recent versions do this automatically */
1315 if (dwc->revision < DWC3_REVISION_194A) {
1316 /* write zeroes to Link Change Request */
1317 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1318 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1319 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1320 }
1321
1322 /* poll until Link State changes to ON */
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05301323 timeout = 1000;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301324
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05301325 while (timeout--) {
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301326 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1327
1328 /* in HS, means ON */
1329 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1330 break;
1331 }
1332
1333 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1334 dev_err(dwc->dev, "failed to send remote wakeup\n");
1335 ret = -EINVAL;
1336 }
1337
1338out:
1339 spin_unlock_irqrestore(&dwc->lock, flags);
1340
1341 return ret;
1342}
1343
1344static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1345 int is_selfpowered)
1346{
1347 struct dwc3 *dwc = gadget_to_dwc(g);
1348 unsigned long flags;
1349
1350 spin_lock_irqsave(&dwc->lock, flags);
1351 dwc->is_selfpowered = !!is_selfpowered;
1352 spin_unlock_irqrestore(&dwc->lock, flags);
1353
1354 return 0;
1355}
1356
1357static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1358{
1359 u32 reg;
1360 u32 timeout = 500;
1361
1362 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1363 if (is_on) {
1364 if (dwc->revision <= DWC3_REVISION_187A) {
1365 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1366 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1367 }
1368
1369 if (dwc->revision >= DWC3_REVISION_194A)
1370 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1371 reg |= DWC3_DCTL_RUN_STOP;
1372
1373 if (dwc->has_hibernation)
1374 reg |= DWC3_DCTL_KEEP_CONNECT;
1375
1376 dwc->pullups_connected = true;
1377 } else {
1378 reg &= ~DWC3_DCTL_RUN_STOP;
1379
1380 if (dwc->has_hibernation && !suspend)
1381 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1382
1383 dwc->pullups_connected = false;
1384 }
1385
1386 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1387
1388 do {
1389 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1390 if (is_on) {
1391 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1392 break;
1393 } else {
1394 if (reg & DWC3_DSTS_DEVCTRLHLT)
1395 break;
1396 }
1397 timeout--;
1398 if (!timeout)
1399 return -ETIMEDOUT;
1400 udelay(1);
1401 } while (1);
1402
1403 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1404 dwc->gadget_driver
1405 ? dwc->gadget_driver->function : "no-function",
1406 is_on ? "connect" : "disconnect");
1407
1408 return 0;
1409}
1410
1411static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1412{
1413 struct dwc3 *dwc = gadget_to_dwc(g);
1414 unsigned long flags;
1415 int ret;
1416
1417 is_on = !!is_on;
1418
1419 spin_lock_irqsave(&dwc->lock, flags);
1420 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1421 spin_unlock_irqrestore(&dwc->lock, flags);
1422
1423 return ret;
1424}
1425
1426static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1427{
1428 u32 reg;
1429
1430 /* Enable all but Start and End of Frame IRQs */
1431 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1432 DWC3_DEVTEN_EVNTOVERFLOWEN |
1433 DWC3_DEVTEN_CMDCMPLTEN |
1434 DWC3_DEVTEN_ERRTICERREN |
1435 DWC3_DEVTEN_WKUPEVTEN |
1436 DWC3_DEVTEN_ULSTCNGEN |
1437 DWC3_DEVTEN_CONNECTDONEEN |
1438 DWC3_DEVTEN_USBRSTEN |
1439 DWC3_DEVTEN_DISCONNEVTEN);
1440
1441 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1442}
1443
1444static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1445{
1446 /* mask all interrupts */
1447 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1448}
1449
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301450static int dwc3_gadget_start(struct usb_gadget *g,
1451 struct usb_gadget_driver *driver)
1452{
1453 struct dwc3 *dwc = gadget_to_dwc(g);
1454 struct dwc3_ep *dep;
1455 unsigned long flags;
1456 int ret = 0;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301457 u32 reg;
1458
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301459 spin_lock_irqsave(&dwc->lock, flags);
1460
1461 if (dwc->gadget_driver) {
1462 dev_err(dwc->dev, "%s is already bound to %s\n",
1463 dwc->gadget.name,
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05301464 dwc->gadget_driver->function);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301465 ret = -EBUSY;
1466 goto err1;
1467 }
1468
1469 dwc->gadget_driver = driver;
1470
1471 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1472 reg &= ~(DWC3_DCFG_SPEED_MASK);
1473
1474 /**
1475 * WORKAROUND: DWC3 revision < 2.20a have an issue
1476 * which would cause metastability state on Run/Stop
1477 * bit if we try to force the IP to USB2-only mode.
1478 *
1479 * Because of that, we cannot configure the IP to any
1480 * speed other than the SuperSpeed
1481 *
1482 * Refers to:
1483 *
1484 * STAR#9000525659: Clock Domain Crossing on DCTL in
1485 * USB 2.0 Mode
1486 */
1487 if (dwc->revision < DWC3_REVISION_220A) {
1488 reg |= DWC3_DCFG_SUPERSPEED;
1489 } else {
1490 switch (dwc->maximum_speed) {
1491 case USB_SPEED_LOW:
1492 reg |= DWC3_DSTS_LOWSPEED;
1493 break;
1494 case USB_SPEED_FULL:
1495 reg |= DWC3_DSTS_FULLSPEED1;
1496 break;
1497 case USB_SPEED_HIGH:
1498 reg |= DWC3_DSTS_HIGHSPEED;
1499 break;
1500 case USB_SPEED_SUPER: /* FALLTHROUGH */
1501 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1502 default:
1503 reg |= DWC3_DSTS_SUPERSPEED;
1504 }
1505 }
1506 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1507
1508 dwc->start_config_issued = false;
1509
1510 /* Start with SuperSpeed Default */
1511 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1512
1513 dep = dwc->eps[0];
1514 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1515 false);
1516 if (ret) {
1517 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1518 goto err2;
1519 }
1520
1521 dep = dwc->eps[1];
1522 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1523 false);
1524 if (ret) {
1525 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1526 goto err3;
1527 }
1528
1529 /* begin to receive SETUP packets */
1530 dwc->ep0state = EP0_SETUP_PHASE;
1531 dwc3_ep0_out_start(dwc);
1532
1533 dwc3_gadget_enable_irq(dwc);
1534
1535 spin_unlock_irqrestore(&dwc->lock, flags);
1536
1537 return 0;
1538
1539err3:
1540 __dwc3_gadget_ep_disable(dwc->eps[0]);
1541
1542err2:
1543 dwc->gadget_driver = NULL;
1544
1545err1:
1546 spin_unlock_irqrestore(&dwc->lock, flags);
1547
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301548 return ret;
1549}
1550
1551static int dwc3_gadget_stop(struct usb_gadget *g)
1552{
1553 struct dwc3 *dwc = gadget_to_dwc(g);
1554 unsigned long flags;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301555
1556 spin_lock_irqsave(&dwc->lock, flags);
1557
1558 dwc3_gadget_disable_irq(dwc);
1559 __dwc3_gadget_ep_disable(dwc->eps[0]);
1560 __dwc3_gadget_ep_disable(dwc->eps[1]);
1561
1562 dwc->gadget_driver = NULL;
1563
1564 spin_unlock_irqrestore(&dwc->lock, flags);
1565
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301566 return 0;
1567}
1568
1569static const struct usb_gadget_ops dwc3_gadget_ops = {
1570 .get_frame = dwc3_gadget_get_frame,
1571 .wakeup = dwc3_gadget_wakeup,
1572 .set_selfpowered = dwc3_gadget_set_selfpowered,
1573 .pullup = dwc3_gadget_pullup,
1574 .udc_start = dwc3_gadget_start,
1575 .udc_stop = dwc3_gadget_stop,
1576};
1577
1578/* -------------------------------------------------------------------------- */
1579
1580static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1581 u8 num, u32 direction)
1582{
1583 struct dwc3_ep *dep;
1584 u8 i;
1585
1586 for (i = 0; i < num; i++) {
1587 u8 epnum = (i << 1) | (!!direction);
1588
1589 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1590 if (!dep)
1591 return -ENOMEM;
1592
1593 dep->dwc = dwc;
1594 dep->number = epnum;
1595 dep->direction = !!direction;
1596 dwc->eps[epnum] = dep;
1597
1598 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1599 (epnum & 1) ? "in" : "out");
1600
1601 dep->endpoint.name = dep->name;
1602
1603 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1604
1605 if (epnum == 0 || epnum == 1) {
1606 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1607 dep->endpoint.maxburst = 1;
1608 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1609 if (!epnum)
1610 dwc->gadget.ep0 = &dep->endpoint;
1611 } else {
1612 int ret;
1613
Lukasz Majewskiafa093b2015-03-03 17:32:14 +01001614 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301615 dep->endpoint.max_streams = 15;
1616 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1617 list_add_tail(&dep->endpoint.ep_list,
1618 &dwc->gadget.ep_list);
1619
1620 ret = dwc3_alloc_trb_pool(dep);
1621 if (ret)
1622 return ret;
1623 }
1624
1625 INIT_LIST_HEAD(&dep->request_list);
1626 INIT_LIST_HEAD(&dep->req_queued);
1627 }
1628
1629 return 0;
1630}
1631
1632static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1633{
1634 int ret;
1635
1636 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1637
1638 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1639 if (ret < 0) {
1640 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1641 return ret;
1642 }
1643
1644 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1645 if (ret < 0) {
1646 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1647 return ret;
1648 }
1649
1650 return 0;
1651}
1652
1653static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1654{
1655 struct dwc3_ep *dep;
1656 u8 epnum;
1657
1658 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1659 dep = dwc->eps[epnum];
1660 if (!dep)
1661 continue;
1662 /*
1663 * Physical endpoints 0 and 1 are special; they form the
1664 * bi-directional USB endpoint 0.
1665 *
1666 * For those two physical endpoints, we don't allocate a TRB
1667 * pool nor do we add them the endpoints list. Due to that, we
1668 * shouldn't do these two operations otherwise we would end up
1669 * with all sorts of bugs when removing dwc3.ko.
1670 */
1671 if (epnum != 0 && epnum != 1) {
1672 dwc3_free_trb_pool(dep);
1673 list_del(&dep->endpoint.ep_list);
1674 }
1675
1676 kfree(dep);
1677 }
1678}
1679
1680/* -------------------------------------------------------------------------- */
1681
1682static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1683 struct dwc3_request *req, struct dwc3_trb *trb,
1684 const struct dwc3_event_depevt *event, int status)
1685{
1686 unsigned int count;
1687 unsigned int s_pkt = 0;
1688 unsigned int trb_status;
1689
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301690 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1691 /*
1692 * We continue despite the error. There is not much we
1693 * can do. If we don't clean it up we loop forever. If
1694 * we skip the TRB then it gets overwritten after a
1695 * while since we use them in a ring buffer. A BUG()
1696 * would help. Lets hope that if this occurs, someone
1697 * fixes the root cause instead of looking away :)
1698 */
1699 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1700 dep->name, trb);
1701 count = trb->size & DWC3_TRB_SIZE_MASK;
1702
1703 if (dep->direction) {
1704 if (count) {
1705 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1706 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1707 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1708 dep->name);
1709 /*
1710 * If missed isoc occurred and there is
1711 * no request queued then issue END
1712 * TRANSFER, so that core generates
1713 * next xfernotready and we will issue
1714 * a fresh START TRANSFER.
1715 * If there are still queued request
1716 * then wait, do not issue either END
1717 * or UPDATE TRANSFER, just attach next
1718 * request in request_list during
1719 * giveback.If any future queued request
1720 * is successfully transferred then we
1721 * will issue UPDATE TRANSFER for all
1722 * request in the request_list.
1723 */
1724 dep->flags |= DWC3_EP_MISSED_ISOC;
1725 } else {
1726 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1727 dep->name);
1728 status = -ECONNRESET;
1729 }
1730 } else {
1731 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1732 }
1733 } else {
1734 if (count && (event->status & DEPEVT_STATUS_SHORT))
1735 s_pkt = 1;
1736 }
1737
1738 /*
1739 * We assume here we will always receive the entire data block
1740 * which we should receive. Meaning, if we program RX to
1741 * receive 4K but we receive only 2K, we assume that's all we
1742 * should receive and we simply bounce the request back to the
1743 * gadget driver for further processing.
1744 */
1745 req->request.actual += req->request.length - count;
1746 if (s_pkt)
1747 return 1;
1748 if ((event->status & DEPEVT_STATUS_LST) &&
1749 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1750 DWC3_TRB_CTRL_HWO)))
1751 return 1;
1752 if ((event->status & DEPEVT_STATUS_IOC) &&
1753 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1754 return 1;
1755 return 0;
1756}
1757
1758static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1759 const struct dwc3_event_depevt *event, int status)
1760{
1761 struct dwc3_request *req;
1762 struct dwc3_trb *trb;
1763 unsigned int slot;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301764
Lukasz Majewski3621b3b2015-03-03 17:32:15 +01001765 req = next_request(&dep->req_queued);
1766 if (!req) {
1767 WARN_ON_ONCE(1);
1768 return 1;
1769 }
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301770
Lukasz Majewski3621b3b2015-03-03 17:32:15 +01001771 slot = req->start_slot;
1772 if ((slot == DWC3_TRB_NUM - 1) &&
1773 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1774 slot++;
1775 slot %= DWC3_TRB_NUM;
1776 trb = &dep->trb_pool[slot];
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05301777
Philipp Tomsichb7bf4a92017-04-06 16:58:52 +02001778 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
Lukasz Majewski3621b3b2015-03-03 17:32:15 +01001779 __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
1780 dwc3_gadget_giveback(dep, req, status);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301781
1782 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1783 list_empty(&dep->req_queued)) {
1784 if (list_empty(&dep->request_list)) {
1785 /*
1786 * If there is no entry in request list then do
1787 * not issue END TRANSFER now. Just set PENDING
1788 * flag, so that END TRANSFER is issued when an
1789 * entry is added into request list.
1790 */
1791 dep->flags = DWC3_EP_PENDING_REQUEST;
1792 } else {
1793 dwc3_stop_active_transfer(dwc, dep->number, true);
1794 dep->flags = DWC3_EP_ENABLED;
1795 }
1796 return 1;
1797 }
1798
1799 return 1;
1800}
1801
1802static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1803 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1804{
1805 unsigned status = 0;
1806 int clean_busy;
1807
1808 if (event->status & DEPEVT_STATUS_BUSERR)
1809 status = -ECONNRESET;
1810
1811 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1812 if (clean_busy)
1813 dep->flags &= ~DWC3_EP_BUSY;
1814
1815 /*
1816 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1817 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1818 */
1819 if (dwc->revision < DWC3_REVISION_183A) {
1820 u32 reg;
1821 int i;
1822
1823 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1824 dep = dwc->eps[i];
1825
1826 if (!(dep->flags & DWC3_EP_ENABLED))
1827 continue;
1828
1829 if (!list_empty(&dep->req_queued))
1830 return;
1831 }
1832
1833 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1834 reg |= dwc->u1u2;
1835 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1836
1837 dwc->u1u2 = 0;
1838 }
1839}
1840
1841static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1842 const struct dwc3_event_depevt *event)
1843{
1844 struct dwc3_ep *dep;
1845 u8 epnum = event->endpoint_number;
1846
1847 dep = dwc->eps[epnum];
1848
1849 if (!(dep->flags & DWC3_EP_ENABLED))
1850 return;
1851
1852 if (epnum == 0 || epnum == 1) {
1853 dwc3_ep0_interrupt(dwc, event);
1854 return;
1855 }
1856
1857 switch (event->endpoint_event) {
1858 case DWC3_DEPEVT_XFERCOMPLETE:
1859 dep->resource_index = 0;
1860
1861 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1862 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1863 dep->name);
1864 return;
1865 }
1866
1867 dwc3_endpoint_transfer_complete(dwc, dep, event);
1868 break;
1869 case DWC3_DEPEVT_XFERINPROGRESS:
1870 dwc3_endpoint_transfer_complete(dwc, dep, event);
1871 break;
1872 case DWC3_DEPEVT_XFERNOTREADY:
1873 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1874 dwc3_gadget_start_isoc(dwc, dep, event);
1875 } else {
1876 int ret;
1877
1878 dev_vdbg(dwc->dev, "%s: reason %s\n",
1879 dep->name, event->status &
1880 DEPEVT_STATUS_TRANSFER_ACTIVE
1881 ? "Transfer Active"
1882 : "Transfer Not Active");
1883
1884 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1885 if (!ret || ret == -EBUSY)
1886 return;
1887
1888 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1889 dep->name);
1890 }
1891
1892 break;
1893 case DWC3_DEPEVT_STREAMEVT:
1894 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1895 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1896 dep->name);
1897 return;
1898 }
1899
1900 switch (event->status) {
1901 case DEPEVT_STREAMEVT_FOUND:
1902 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1903 event->parameters);
1904
1905 break;
1906 case DEPEVT_STREAMEVT_NOTFOUND:
1907 /* FALLTHROUGH */
1908 default:
1909 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1910 }
1911 break;
1912 case DWC3_DEPEVT_RXTXFIFOEVT:
1913 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1914 break;
1915 case DWC3_DEPEVT_EPCMDCMPLT:
1916 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1917 break;
1918 }
1919}
1920
1921static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1922{
1923 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1924 spin_unlock(&dwc->lock);
1925 dwc->gadget_driver->disconnect(&dwc->gadget);
1926 spin_lock(&dwc->lock);
1927 }
1928}
1929
1930static void dwc3_suspend_gadget(struct dwc3 *dwc)
1931{
1932 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1933 spin_unlock(&dwc->lock);
1934 dwc->gadget_driver->suspend(&dwc->gadget);
1935 spin_lock(&dwc->lock);
1936 }
1937}
1938
1939static void dwc3_resume_gadget(struct dwc3 *dwc)
1940{
1941 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1942 spin_unlock(&dwc->lock);
1943 dwc->gadget_driver->resume(&dwc->gadget);
1944 }
1945}
1946
1947static void dwc3_reset_gadget(struct dwc3 *dwc)
1948{
1949 if (!dwc->gadget_driver)
1950 return;
1951
1952 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1953 spin_unlock(&dwc->lock);
1954 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1955 spin_lock(&dwc->lock);
1956 }
1957}
1958
1959static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1960{
1961 struct dwc3_ep *dep;
1962 struct dwc3_gadget_ep_cmd_params params;
1963 u32 cmd;
1964 int ret;
1965
1966 dep = dwc->eps[epnum];
1967
1968 if (!dep->resource_index)
1969 return;
1970
1971 /*
1972 * NOTICE: We are violating what the Databook says about the
1973 * EndTransfer command. Ideally we would _always_ wait for the
1974 * EndTransfer Command Completion IRQ, but that's causing too
1975 * much trouble synchronizing between us and gadget driver.
1976 *
1977 * We have discussed this with the IP Provider and it was
1978 * suggested to giveback all requests here, but give HW some
1979 * extra time to synchronize with the interconnect. We're using
1980 * an arbitraty 100us delay for that.
1981 *
1982 * Note also that a similar handling was tested by Synopsys
1983 * (thanks a lot Paul) and nothing bad has come out of it.
1984 * In short, what we're doing is:
1985 *
1986 * - Issue EndTransfer WITH CMDIOC bit set
1987 * - Wait 100us
1988 */
1989
1990 cmd = DWC3_DEPCMD_ENDTRANSFER;
1991 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1992 cmd |= DWC3_DEPCMD_CMDIOC;
1993 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1994 memset(&params, 0, sizeof(params));
1995 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1996 WARN_ON_ONCE(ret);
1997 dep->resource_index = 0;
1998 dep->flags &= ~DWC3_EP_BUSY;
1999 udelay(100);
2000}
2001
2002static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2003{
2004 u32 epnum;
2005
2006 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2007 struct dwc3_ep *dep;
2008
2009 dep = dwc->eps[epnum];
2010 if (!dep)
2011 continue;
2012
2013 if (!(dep->flags & DWC3_EP_ENABLED))
2014 continue;
2015
2016 dwc3_remove_requests(dwc, dep);
2017 }
2018}
2019
2020static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2021{
2022 u32 epnum;
2023
2024 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2025 struct dwc3_ep *dep;
2026 struct dwc3_gadget_ep_cmd_params params;
2027 int ret;
2028
2029 dep = dwc->eps[epnum];
2030 if (!dep)
2031 continue;
2032
2033 if (!(dep->flags & DWC3_EP_STALL))
2034 continue;
2035
2036 dep->flags &= ~DWC3_EP_STALL;
2037
2038 memset(&params, 0, sizeof(params));
2039 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2040 DWC3_DEPCMD_CLEARSTALL, &params);
2041 WARN_ON_ONCE(ret);
2042 }
2043}
2044
2045static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2046{
2047 int reg;
2048
2049 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2050 reg &= ~DWC3_DCTL_INITU1ENA;
2051 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2052
2053 reg &= ~DWC3_DCTL_INITU2ENA;
2054 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2055
2056 dwc3_disconnect_gadget(dwc);
2057 dwc->start_config_issued = false;
2058
2059 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2060 dwc->setup_packet_pending = false;
2061 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2062}
2063
2064static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2065{
2066 u32 reg;
2067
2068 /*
2069 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2070 * would cause a missing Disconnect Event if there's a
2071 * pending Setup Packet in the FIFO.
2072 *
2073 * There's no suggested workaround on the official Bug
2074 * report, which states that "unless the driver/application
2075 * is doing any special handling of a disconnect event,
2076 * there is no functional issue".
2077 *
2078 * Unfortunately, it turns out that we _do_ some special
2079 * handling of a disconnect event, namely complete all
2080 * pending transfers, notify gadget driver of the
2081 * disconnection, and so on.
2082 *
2083 * Our suggested workaround is to follow the Disconnect
2084 * Event steps here, instead, based on a setup_packet_pending
2085 * flag. Such flag gets set whenever we have a XferNotReady
2086 * event on EP0 and gets cleared on XferComplete for the
2087 * same endpoint.
2088 *
2089 * Refers to:
2090 *
2091 * STAR#9000466709: RTL: Device : Disconnect event not
2092 * generated if setup packet pending in FIFO
2093 */
2094 if (dwc->revision < DWC3_REVISION_188A) {
2095 if (dwc->setup_packet_pending)
2096 dwc3_gadget_disconnect_interrupt(dwc);
2097 }
2098
2099 dwc3_reset_gadget(dwc);
2100
2101 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2102 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2103 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2104 dwc->test_mode = false;
2105
2106 dwc3_stop_active_transfers(dwc);
2107 dwc3_clear_stall_all_ep(dwc);
2108 dwc->start_config_issued = false;
2109
2110 /* Reset device address to zero */
2111 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2112 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2113 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2114}
2115
2116static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2117{
2118 u32 reg;
2119 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2120
2121 /*
2122 * We change the clock only at SS but I dunno why I would want to do
2123 * this. Maybe it becomes part of the power saving plan.
2124 */
2125
2126 if (speed != DWC3_DSTS_SUPERSPEED)
2127 return;
2128
2129 /*
2130 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2131 * each time on Connect Done.
2132 */
2133 if (!usb30_clock)
2134 return;
2135
2136 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2137 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2138 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2139}
2140
2141static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2142{
2143 struct dwc3_ep *dep;
2144 int ret;
2145 u32 reg;
2146 u8 speed;
2147
2148 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2149 speed = reg & DWC3_DSTS_CONNECTSPD;
2150 dwc->speed = speed;
2151
2152 dwc3_update_ram_clk_sel(dwc, speed);
2153
2154 switch (speed) {
2155 case DWC3_DCFG_SUPERSPEED:
2156 /*
2157 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2158 * would cause a missing USB3 Reset event.
2159 *
2160 * In such situations, we should force a USB3 Reset
2161 * event by calling our dwc3_gadget_reset_interrupt()
2162 * routine.
2163 *
2164 * Refers to:
2165 *
2166 * STAR#9000483510: RTL: SS : USB3 reset event may
2167 * not be generated always when the link enters poll
2168 */
2169 if (dwc->revision < DWC3_REVISION_190A)
2170 dwc3_gadget_reset_interrupt(dwc);
2171
2172 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2173 dwc->gadget.ep0->maxpacket = 512;
2174 dwc->gadget.speed = USB_SPEED_SUPER;
2175 break;
2176 case DWC3_DCFG_HIGHSPEED:
2177 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2178 dwc->gadget.ep0->maxpacket = 64;
2179 dwc->gadget.speed = USB_SPEED_HIGH;
2180 break;
2181 case DWC3_DCFG_FULLSPEED2:
2182 case DWC3_DCFG_FULLSPEED1:
2183 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2184 dwc->gadget.ep0->maxpacket = 64;
2185 dwc->gadget.speed = USB_SPEED_FULL;
2186 break;
2187 case DWC3_DCFG_LOWSPEED:
2188 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2189 dwc->gadget.ep0->maxpacket = 8;
2190 dwc->gadget.speed = USB_SPEED_LOW;
2191 break;
2192 }
2193
2194 /* Enable USB2 LPM Capability */
2195
2196 if ((dwc->revision > DWC3_REVISION_194A)
2197 && (speed != DWC3_DCFG_SUPERSPEED)) {
2198 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2199 reg |= DWC3_DCFG_LPM_CAP;
2200 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2201
2202 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2203 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2204
2205 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2206
2207 /*
2208 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2209 * DCFG.LPMCap is set, core responses with an ACK and the
2210 * BESL value in the LPM token is less than or equal to LPM
2211 * NYET threshold.
2212 */
Wolfgang Denk0cf207e2021-09-27 17:42:39 +02002213 if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302214 WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302215
2216 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2217 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2218
2219 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2220 } else {
2221 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2222 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2223 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2224 }
2225
2226 dep = dwc->eps[0];
2227 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2228 false);
2229 if (ret) {
2230 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2231 return;
2232 }
2233
2234 dep = dwc->eps[1];
2235 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2236 false);
2237 if (ret) {
2238 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2239 return;
2240 }
2241
2242 /*
2243 * Configure PHY via GUSB3PIPECTLn if required.
2244 *
2245 * Update GTXFIFOSIZn
2246 *
2247 * In both cases reset values should be sufficient.
2248 */
2249}
2250
2251static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2252{
2253 /*
2254 * TODO take core out of low power mode when that's
2255 * implemented.
2256 */
2257
2258 dwc->gadget_driver->resume(&dwc->gadget);
2259}
2260
2261static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2262 unsigned int evtinfo)
2263{
2264 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2265 unsigned int pwropt;
2266
2267 /*
2268 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2269 * Hibernation mode enabled which would show up when device detects
2270 * host-initiated U3 exit.
2271 *
2272 * In that case, device will generate a Link State Change Interrupt
2273 * from U3 to RESUME which is only necessary if Hibernation is
2274 * configured in.
2275 *
2276 * There are no functional changes due to such spurious event and we
2277 * just need to ignore it.
2278 *
2279 * Refers to:
2280 *
2281 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2282 * operational mode
2283 */
2284 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2285 if ((dwc->revision < DWC3_REVISION_250A) &&
2286 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2287 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2288 (next == DWC3_LINK_STATE_RESUME)) {
2289 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2290 return;
2291 }
2292 }
2293
2294 /*
2295 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2296 * on the link partner, the USB session might do multiple entry/exit
2297 * of low power states before a transfer takes place.
2298 *
2299 * Due to this problem, we might experience lower throughput. The
2300 * suggested workaround is to disable DCTL[12:9] bits if we're
2301 * transitioning from U1/U2 to U0 and enable those bits again
2302 * after a transfer completes and there are no pending transfers
2303 * on any of the enabled endpoints.
2304 *
2305 * This is the first half of that workaround.
2306 *
2307 * Refers to:
2308 *
2309 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2310 * core send LGO_Ux entering U0
2311 */
2312 if (dwc->revision < DWC3_REVISION_183A) {
2313 if (next == DWC3_LINK_STATE_U0) {
2314 u32 u1u2;
2315 u32 reg;
2316
2317 switch (dwc->link_state) {
2318 case DWC3_LINK_STATE_U1:
2319 case DWC3_LINK_STATE_U2:
2320 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2321 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2322 | DWC3_DCTL_ACCEPTU2ENA
2323 | DWC3_DCTL_INITU1ENA
2324 | DWC3_DCTL_ACCEPTU1ENA);
2325
2326 if (!dwc->u1u2)
2327 dwc->u1u2 = reg & u1u2;
2328
2329 reg &= ~u1u2;
2330
2331 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2332 break;
2333 default:
2334 /* do nothing */
2335 break;
2336 }
2337 }
2338 }
2339
2340 switch (next) {
2341 case DWC3_LINK_STATE_U1:
2342 if (dwc->speed == USB_SPEED_SUPER)
2343 dwc3_suspend_gadget(dwc);
2344 break;
2345 case DWC3_LINK_STATE_U2:
2346 case DWC3_LINK_STATE_U3:
2347 dwc3_suspend_gadget(dwc);
2348 break;
2349 case DWC3_LINK_STATE_RESUME:
2350 dwc3_resume_gadget(dwc);
2351 break;
2352 default:
2353 /* do nothing */
2354 break;
2355 }
2356
2357 dwc->link_state = next;
2358}
2359
2360static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2361 unsigned int evtinfo)
2362{
Lukasz Majewski2252d152015-03-03 17:32:08 +01002363 unsigned int is_ss = evtinfo & (1UL << 4);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302364
2365 /**
2366 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2367 * have a known issue which can cause USB CV TD.9.23 to fail
2368 * randomly.
2369 *
2370 * Because of this issue, core could generate bogus hibernation
2371 * events which SW needs to ignore.
2372 *
2373 * Refers to:
2374 *
2375 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2376 * Device Fallback from SuperSpeed
2377 */
2378 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2379 return;
2380
2381 /* enter hibernation here */
2382}
2383
2384static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2385 const struct dwc3_event_devt *event)
2386{
2387 switch (event->type) {
2388 case DWC3_DEVICE_EVENT_DISCONNECT:
2389 dwc3_gadget_disconnect_interrupt(dwc);
2390 break;
2391 case DWC3_DEVICE_EVENT_RESET:
2392 dwc3_gadget_reset_interrupt(dwc);
2393 break;
2394 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2395 dwc3_gadget_conndone_interrupt(dwc);
2396 break;
2397 case DWC3_DEVICE_EVENT_WAKEUP:
2398 dwc3_gadget_wakeup_interrupt(dwc);
2399 break;
2400 case DWC3_DEVICE_EVENT_HIBER_REQ:
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302401 if (!dwc->has_hibernation) {
2402 WARN(1 ,"unexpected hibernation event\n");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302403 break;
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302404 }
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302405 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2406 break;
2407 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2408 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2409 break;
2410 case DWC3_DEVICE_EVENT_EOPF:
2411 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2412 break;
2413 case DWC3_DEVICE_EVENT_SOF:
2414 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2415 break;
2416 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2417 dev_vdbg(dwc->dev, "Erratic Error\n");
2418 break;
2419 case DWC3_DEVICE_EVENT_CMD_CMPL:
2420 dev_vdbg(dwc->dev, "Command Complete\n");
2421 break;
2422 case DWC3_DEVICE_EVENT_OVERFLOW:
2423 dev_vdbg(dwc->dev, "Overflow\n");
2424 break;
2425 default:
2426 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2427 }
2428}
2429
2430static void dwc3_process_event_entry(struct dwc3 *dwc,
2431 const union dwc3_event *event)
2432{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302433 /* Endpoint IRQ, handle it and return early */
2434 if (event->type.is_devspec == 0) {
2435 /* depevt */
2436 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2437 }
2438
2439 switch (event->type.type) {
2440 case DWC3_EVENT_TYPE_DEV:
2441 dwc3_gadget_interrupt(dwc, &event->devt);
2442 break;
2443 /* REVISIT what to do with Carkit and I2C events ? */
2444 default:
2445 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2446 }
2447}
2448
2449static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2450{
2451 struct dwc3_event_buffer *evt;
2452 irqreturn_t ret = IRQ_NONE;
2453 int left;
2454 u32 reg;
2455
2456 evt = dwc->ev_buffs[buf];
2457 left = evt->count;
2458
2459 if (!(evt->flags & DWC3_EVENT_PENDING))
2460 return IRQ_NONE;
2461
2462 while (left > 0) {
2463 union dwc3_event event;
2464
2465 event.raw = *(u32 *) (evt->buf + evt->lpos);
2466
2467 dwc3_process_event_entry(dwc, &event);
2468
2469 /*
2470 * FIXME we wrap around correctly to the next entry as
2471 * almost all entries are 4 bytes in size. There is one
2472 * entry which has 12 bytes which is a regular entry
2473 * followed by 8 bytes data. ATM I don't know how
2474 * things are organized if we get next to the a
2475 * boundary so I worry about that once we try to handle
2476 * that.
2477 */
2478 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2479 left -= 4;
2480
2481 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2482 }
2483
2484 evt->count = 0;
2485 evt->flags &= ~DWC3_EVENT_PENDING;
2486 ret = IRQ_HANDLED;
2487
2488 /* Unmask interrupt */
2489 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2490 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2491 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2492
2493 return ret;
2494}
2495
2496static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2497{
2498 struct dwc3 *dwc = _dwc;
2499 unsigned long flags;
2500 irqreturn_t ret = IRQ_NONE;
2501 int i;
2502
2503 spin_lock_irqsave(&dwc->lock, flags);
2504
2505 for (i = 0; i < dwc->num_event_buffers; i++)
2506 ret |= dwc3_process_event_buf(dwc, i);
2507
2508 spin_unlock_irqrestore(&dwc->lock, flags);
2509
2510 return ret;
2511}
2512
2513static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2514{
2515 struct dwc3_event_buffer *evt;
2516 u32 count;
2517 u32 reg;
2518
2519 evt = dwc->ev_buffs[buf];
2520
2521 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2522 count &= DWC3_GEVNTCOUNT_MASK;
2523 if (!count)
2524 return IRQ_NONE;
2525
2526 evt->count = count;
2527 evt->flags |= DWC3_EVENT_PENDING;
2528
2529 /* Mask interrupt */
2530 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2531 reg |= DWC3_GEVNTSIZ_INTMASK;
2532 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2533
2534 return IRQ_WAKE_THREAD;
2535}
2536
2537static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2538{
2539 struct dwc3 *dwc = _dwc;
2540 int i;
2541 irqreturn_t ret = IRQ_NONE;
2542
2543 spin_lock(&dwc->lock);
2544
2545 for (i = 0; i < dwc->num_event_buffers; i++) {
2546 irqreturn_t status;
2547
2548 status = dwc3_check_event_buf(dwc, i);
2549 if (status == IRQ_WAKE_THREAD)
2550 ret = status;
2551 }
2552
2553 spin_unlock(&dwc->lock);
2554
2555 return ret;
2556}
2557
2558/**
2559 * dwc3_gadget_init - Initializes gadget related registers
2560 * @dwc: pointer to our controller context structure
2561 *
2562 * Returns 0 on success otherwise negative errno.
2563 */
2564int dwc3_gadget_init(struct dwc3 *dwc)
2565{
2566 int ret;
2567
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302568 dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2569 (unsigned long *)&dwc->ctrl_req_addr);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302570 if (!dwc->ctrl_req) {
2571 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2572 ret = -ENOMEM;
2573 goto err0;
2574 }
2575
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +05302576 dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302577 (unsigned long *)&dwc->ep0_trb_addr);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302578 if (!dwc->ep0_trb) {
2579 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2580 ret = -ENOMEM;
2581 goto err1;
2582 }
2583
Kishon Vijay Abraham I526a50f2015-02-23 18:40:13 +05302584 dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2585 DWC3_EP0_BOUNCE_SIZE);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302586 if (!dwc->setup_buf) {
2587 ret = -ENOMEM;
2588 goto err2;
2589 }
2590
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302591 dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2592 (unsigned long *)&dwc->ep0_bounce_addr);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302593 if (!dwc->ep0_bounce) {
2594 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2595 ret = -ENOMEM;
2596 goto err3;
2597 }
2598
2599 dwc->gadget.ops = &dwc3_gadget_ops;
2600 dwc->gadget.max_speed = USB_SPEED_SUPER;
2601 dwc->gadget.speed = USB_SPEED_UNKNOWN;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302602 dwc->gadget.name = "dwc3-gadget";
2603
2604 /*
2605 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2606 * on ep out.
2607 */
2608 dwc->gadget.quirk_ep_out_aligned_size = true;
2609
2610 /*
2611 * REVISIT: Here we should clear all pending IRQs to be
2612 * sure we're starting from a well known location.
2613 */
2614
2615 ret = dwc3_gadget_init_endpoints(dwc);
2616 if (ret)
2617 goto err4;
2618
Mugunthan V N23ba2d62018-05-18 13:15:04 +02002619 ret = usb_add_gadget_udc((struct device *)dwc->dev, &dwc->gadget);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302620 if (ret) {
2621 dev_err(dwc->dev, "failed to register udc\n");
2622 goto err4;
2623 }
2624
2625 return 0;
2626
2627err4:
2628 dwc3_gadget_free_endpoints(dwc);
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302629 dma_free_coherent(dwc->ep0_bounce);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302630
2631err3:
2632 kfree(dwc->setup_buf);
2633
2634err2:
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302635 dma_free_coherent(dwc->ep0_trb);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302636
2637err1:
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302638 dma_free_coherent(dwc->ctrl_req);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302639
2640err0:
2641 return ret;
2642}
2643
2644/* -------------------------------------------------------------------------- */
2645
2646void dwc3_gadget_exit(struct dwc3 *dwc)
2647{
2648 usb_del_gadget_udc(&dwc->gadget);
2649
2650 dwc3_gadget_free_endpoints(dwc);
2651
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302652 dma_free_coherent(dwc->ep0_bounce);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302653
2654 kfree(dwc->setup_buf);
2655
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302656 dma_free_coherent(dwc->ep0_trb);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302657
Kishon Vijay Abraham I747a0a52015-02-23 18:39:58 +05302658 dma_free_coherent(dwc->ctrl_req);
2659}
2660
2661/**
2662 * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2663 * @dwc: struct dwce *
2664 *
2665 * Handles ep0 and gadget interrupt
2666 *
2667 * Should be called from dwc3 core.
2668 */
2669void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2670{
Marek Szyprowski137f7c52015-03-03 17:32:12 +01002671 int ret = dwc3_interrupt(0, dwc);
2672
2673 if (ret == IRQ_WAKE_THREAD) {
2674 int i;
2675 struct dwc3_event_buffer *evt;
2676
Philipp Tomsich889239d2017-04-06 16:58:53 +02002677 dwc3_thread_interrupt(0, dwc);
2678
2679 /* Clean + Invalidate the buffers after touching them */
Marek Szyprowski137f7c52015-03-03 17:32:12 +01002680 for (i = 0; i < dwc->num_event_buffers; i++) {
2681 evt = dwc->ev_buffs[i];
Philipp Tomsichb7bf4a92017-04-06 16:58:52 +02002682 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
Marek Szyprowski137f7c52015-03-03 17:32:12 +01002683 }
Marek Szyprowski137f7c52015-03-03 17:32:12 +01002684 }
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302685}