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Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +02001/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 *
7 * (C) Copyright 2009
8 * Frederik Kriewitz <frederik@kriewitz.eu>
9 *
10 * Configuration settings for the DevKit8000 board.
11 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020017
18/* High Level Configuration Options */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020019#define CONFIG_OMAP 1 /* in a TI OMAP core */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020020#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
Simon Schwarz2d52a9a2012-03-15 04:01:40 +000021#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
Marek Vasut308252a2012-07-21 05:02:23 +000022#define CONFIG_OMAP_GPIO
Lokesh Vutla806d2792013-07-30 11:36:30 +053023#define CONFIG_OMAP_COMMON
Marek Vasut308252a2012-07-21 05:02:23 +000024
Simon Schwarz5183b7e2011-12-05 23:16:28 +000025/*
26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
27 * 64 bytes before this address should be set aside for u-boot.img's
28 * header. That is 0x800FFFC0--0x80100000 should not be used for any
29 * other needs.
30 */
31#define CONFIG_SYS_TEXT_BASE 0x80100000
Thomas Weber66fca012010-10-18 15:38:15 +020032
Vaibhav Hiremathcae377b2010-06-07 15:20:34 -040033#define CONFIG_SDRC /* The chip has SDRC controller */
34
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020035#include <asm/arch/cpu.h> /* get chip and board defs */
36#include <asm/arch/omap3.h>
37
38/* Display CPU and Board information */
39#define CONFIG_DISPLAY_CPUINFO 1
40#define CONFIG_DISPLAY_BOARDINFO 1
41
42/* Clock Defines */
43#define V_OSCK 26000000 /* Clock output from T2 */
44#define V_SCLK (V_OSCK >> 1)
45
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020046#define CONFIG_MISC_INIT_R
47
48#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
49#define CONFIG_SETUP_MEMORY_TAGS 1
50#define CONFIG_INITRD_TAG 1
51#define CONFIG_REVISION_TAG 1
52
Grant Likely2fa8ca92011-03-28 09:59:07 +000053#define CONFIG_OF_LIBFDT 1
54
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020055/* Size of malloc() pool */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040056#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020057 /* Sector */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040058#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020059
60/* Hardware drivers */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020061/* DM9000 */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020062#define CONFIG_NET_RETRY_COUNT 20
63#define CONFIG_DRIVER_DM9000 1
64#define CONFIG_DM9000_BASE 0x2c000000
65#define DM9000_IO CONFIG_DM9000_BASE
66#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
67#define CONFIG_DM9000_USE_16BIT 1
68#define CONFIG_DM9000_NO_SROM 1
69#undef CONFIG_DM9000_DEBUG
70
71/* NS16550 Configuration */
72#define CONFIG_SYS_NS16550
73#define CONFIG_SYS_NS16550_SERIAL
74#define CONFIG_SYS_NS16550_REG_SIZE (-4)
75#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
76
77/* select serial console configuration */
78#define CONFIG_CONS_INDEX 3
79#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
80#define CONFIG_SERIAL3 3
81#define CONFIG_BAUDRATE 115200
82#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
83 115200}
84
85/* MMC */
Tom Rinif4085012011-09-03 21:52:45 -040086#define CONFIG_GENERIC_MMC 1
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020087#define CONFIG_MMC 1
Tom Rinif4085012011-09-03 21:52:45 -040088#define CONFIG_OMAP_HSMMC 1
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020089#define CONFIG_DOS_PARTITION 1
90
91/* I2C */
Heiko Schocher6789e842013-10-22 11:03:18 +020092#define CONFIG_SYS_I2C
93#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
94#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
95#define CONFIG_SYS_I2C_OMAP34XX
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020096
97/* TWL4030 */
98#define CONFIG_TWL4030_POWER 1
99#define CONFIG_TWL4030_LED 1
100
101/* Board NAND Info */
102#define CONFIG_SYS_NO_FLASH /* no NOR flash */
103#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
104#define MTDIDS_DEFAULT "nand0=nand"
105#define MTDPARTS_DEFAULT "mtdparts=nand:" \
106 "512k(x-loader)," \
107 "1920k(u-boot)," \
108 "128k(u-boot-env)," \
109 "4m(kernel)," \
110 "-(fs)"
111
112#define CONFIG_NAND_OMAP_GPMC
113#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
114 /* to access nand */
115#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
116 /* to access nand at */
117 /* CS0 */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200118#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
119 /* devices */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200120#define CONFIG_JFFS2_NAND
121/* nand device jffs2 lives on */
122#define CONFIG_JFFS2_DEV "nand0"
123/* start of jffs2 partition */
124#define CONFIG_JFFS2_PART_OFFSET 0x680000
125#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
126 /* partition */
127
128/* commands to include */
129#include <config_cmd_default.h>
130
131#define CONFIG_CMD_DHCP /* DHCP support */
132#define CONFIG_CMD_EXT2 /* EXT2 Support */
133#define CONFIG_CMD_FAT /* FAT support */
134#define CONFIG_CMD_I2C /* I2C serial bus support */
135#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
136#define CONFIG_CMD_MMC /* MMC support */
137#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
138#define CONFIG_CMD_NAND /* NAND support */
139#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
140
141#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
142#undef CONFIG_CMD_IMI /* iminfo */
143
144/* BOOTP/DHCP options */
145#define CONFIG_BOOTP_SUBNETMASK
146#define CONFIG_BOOTP_GATEWAY
147#define CONFIG_BOOTP_HOSTNAME
148#define CONFIG_BOOTP_NISDOMAIN
149#define CONFIG_BOOTP_BOOTPATH
150#define CONFIG_BOOTP_BOOTFILESIZE
151#define CONFIG_BOOTP_DNS
152#define CONFIG_BOOTP_DNS2
153#define CONFIG_BOOTP_SEND_HOSTNAME
154#define CONFIG_BOOTP_NTPSERVER
155#define CONFIG_BOOTP_TIMEOFFSET
156#undef CONFIG_BOOTP_VENDOREX
157
158/* Environment information */
159#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
160
161#define CONFIG_BOOTDELAY 3
162
163#define CONFIG_EXTRA_ENV_SETTINGS \
164 "loadaddr=0x82000000\0" \
Thomas Weber2d76da22011-09-18 22:43:58 +0000165 "console=ttyO2,115200n8\0" \
Tom Rinif4085012011-09-03 21:52:45 -0400166 "mmcdev=0\0" \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200167 "vram=12M\0" \
168 "dvimode=1024x768MR-16@60\0" \
169 "defaultdisplay=dvi\0" \
170 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
171 "kernelopts=rw\0" \
172 "commonargs=" \
173 "setenv bootargs console=${console} " \
174 "vram=${vram} " \
175 "omapfb.mode=dvi:${dvimode} " \
176 "omapdss.def_disp=${defaultdisplay}\0" \
177 "mmcargs=" \
178 "run commonargs; " \
179 "setenv bootargs ${bootargs} " \
180 "root=/dev/mmcblk0p2 " \
Andreas Bießmannb72db202012-08-30 23:53:32 +0000181 "rootwait " \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200182 "${kernelopts}\0" \
183 "nandargs=" \
184 "run commonargs; " \
185 "setenv bootargs ${bootargs} " \
186 "omapfb.mode=dvi:${dvimode} " \
187 "omapdss.def_disp=${defaultdisplay} " \
188 "root=/dev/mtdblock4 " \
189 "rootfstype=jffs2 " \
190 "${kernelopts}\0" \
191 "netargs=" \
192 "run commonargs; " \
193 "setenv bootargs ${bootargs} " \
194 "root=/dev/nfs " \
195 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
196 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
197 "${kernelopts} " \
198 "dnsip1=${dnsip} " \
199 "dnsip2=${dnsip2}\0" \
Tom Rinif4085012011-09-03 21:52:45 -0400200 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200201 "bootscript=echo Running bootscript from mmc ...; " \
202 "source ${loadaddr}\0" \
Tom Rinif4085012011-09-03 21:52:45 -0400203 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200204 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
205 "mmcboot=echo Booting from mmc ...; " \
206 "run mmcargs; " \
207 "bootm ${loadaddr}\0" \
208 "nandboot=echo Booting from nand ...; " \
209 "run nandargs; " \
210 "nand read ${loadaddr} 280000 400000; " \
211 "bootm ${loadaddr}\0" \
212 "netboot=echo Booting from network ...; " \
213 "dhcp ${loadaddr}; " \
214 "run netargs; " \
215 "bootm ${loadaddr}\0" \
Andrew Bradford66968112012-10-01 05:06:52 +0000216 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200217 "if run loadbootscript; then " \
218 "run bootscript; " \
219 "else " \
220 "if run loaduimage; then " \
221 "run mmcboot; " \
222 "else run nandboot; " \
223 "fi; " \
224 "fi; " \
225 "else run nandboot; fi\0"
226
227
228#define CONFIG_BOOTCOMMAND "run autoboot"
229
230/* Miscellaneous configurable options */
231#define CONFIG_SYS_LONGHELP /* undef to save memory */
232#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
233#define CONFIG_AUTO_COMPLETE 1
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200234#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
235#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
236/* Print Buffer Size */
237#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
238 sizeof(CONFIG_SYS_PROMPT) + 16)
239#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
240
241/* Boot Argument Buffer Size */
242#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
243
244#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
245#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
246 0x01000000) /* 16MB */
247
248#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
249
250/*
251 * OMAP3 has 12 GP timers, they can be driven by the system clock
252 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
253 * This rate is divided by a local divisor.
254 */
255#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
256#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200257
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200258/* Physical Memory Map */
259#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
260#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200261#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
262
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200263/* NAND and environment organization */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400264#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200265
266#define CONFIG_ENV_IS_IN_NAND 1
267#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
268
Luca Ceresoli6cbec7b2011-04-20 11:02:05 -0400269#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200270
Thomas Weber66fca012010-10-18 15:38:15 +0200271#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Thomas Weber30f305c2010-11-18 08:45:25 +0100272#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
273#define CONFIG_SYS_INIT_RAM_SIZE 0x800
274#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk93e14592013-10-04 17:43:24 +0200275 CONFIG_SYS_INIT_RAM_SIZE - \
276 GENERATED_GBL_DATA_SIZE)
Thomas Weber66fca012010-10-18 15:38:15 +0200277
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400278/* SRAM config */
279#define CONFIG_SYS_SRAM_START 0x40200000
280#define CONFIG_SYS_SRAM_SIZE 0x10000
281
282/* Defines for SPL */
Tom Rini47f7bca2012-08-13 12:03:19 -0700283#define CONFIG_SPL_FRAMEWORK
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400284#define CONFIG_SPL_NAND_SIMPLE
285
286#define CONFIG_SPL_LIBCOMMON_SUPPORT
287#define CONFIG_SPL_LIBDISK_SUPPORT
Tom Riniee08a822011-11-23 05:13:06 +0000288#define CONFIG_SPL_BOARD_INIT
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400289#define CONFIG_SPL_I2C_SUPPORT
290#define CONFIG_SPL_LIBGENERIC_SUPPORT
291#define CONFIG_SPL_SERIAL_SUPPORT
Marek Vasut16e41c82012-07-21 05:02:27 +0000292#define CONFIG_SPL_GPIO_SUPPORT
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400293#define CONFIG_SPL_POWER_SUPPORT
294#define CONFIG_SPL_NAND_SUPPORT
Scott Wood6f2f01b2012-09-20 19:09:07 -0500295#define CONFIG_SPL_NAND_BASE
296#define CONFIG_SPL_NAND_DRIVERS
297#define CONFIG_SPL_NAND_ECC
Simon Schwarz99154712011-09-30 00:41:34 +0000298#define CONFIG_SPL_MMC_SUPPORT
299#define CONFIG_SPL_FAT_SUPPORT
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400300#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
Simon Schwarz99154712011-09-30 00:41:34 +0000301#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
302#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
303#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400304
305#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
Tom Rinie0820cc2012-05-08 07:29:31 +0000306#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400307#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
308
Simon Schwarz2d52a9a2012-03-15 04:01:40 +0000309#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400310#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
311
312/* NAND boot config */
pekon guptab80a6602014-05-06 00:46:19 +0530313#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
Tom Rinic471ccb2011-11-09 16:40:04 -0500314#define CONFIG_SYS_NAND_5_ADDR_CYCLE
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400315#define CONFIG_SYS_NAND_PAGE_COUNT 64
316#define CONFIG_SYS_NAND_PAGE_SIZE 2048
317#define CONFIG_SYS_NAND_OOBSIZE 64
318#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
319#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
320#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
321 10, 11, 12, 13}
322
323#define CONFIG_SYS_NAND_ECCSIZE 512
324#define CONFIG_SYS_NAND_ECCBYTES 3
pekon gupta3f719062013-11-18 19:03:01 +0530325#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400326
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400327#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
328
329#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
330#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
331
Simon Schwarz5183b7e2011-12-05 23:16:28 +0000332#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
Tom Riniba75a812011-10-18 10:47:22 -0700333#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
334
Simon Schwarzd38bc972012-03-15 04:01:35 +0000335/* SPL OS boot options */
Simon Schwarz2d52a9a2012-03-15 04:01:40 +0000336#define CONFIG_SPL_OS_BOOT
Simon Schwarz2d52a9a2012-03-15 04:01:40 +0000337
Simon Schwarzd38bc972012-03-15 04:01:35 +0000338#define CONFIG_CMD_SPL
339#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
340#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
341 0x400000)
342#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
Tom Rinib6144df2013-06-07 14:16:43 -0400343
344#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage"
345#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args"
346
347#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
348#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
349#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
350
Simon Schwarzd38bc972012-03-15 04:01:35 +0000351#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
352
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200353#endif /* __CONFIG_H */