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Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +02001/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 *
7 * (C) Copyright 2009
8 * Frederik Kriewitz <frederik@kriewitz.eu>
9 *
10 * Configuration settings for the DevKit8000 board.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020033
34/* High Level Configuration Options */
35#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
36#define CONFIG_OMAP 1 /* in a TI OMAP core */
37#define CONFIG_OMAP34XX 1 /* which is a 34XX */
38#define CONFIG_OMAP3430 1 /* which is in a 3430 */
39#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
40
41#include <asm/arch/cpu.h> /* get chip and board defs */
42#include <asm/arch/omap3.h>
43
44/* Display CPU and Board information */
45#define CONFIG_DISPLAY_CPUINFO 1
46#define CONFIG_DISPLAY_BOARDINFO 1
47
48/* Clock Defines */
49#define V_OSCK 26000000 /* Clock output from T2 */
50#define V_SCLK (V_OSCK >> 1)
51
52#undef CONFIG_USE_IRQ /* no support for IRQs */
53#define CONFIG_MISC_INIT_R
54
55#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
56#define CONFIG_SETUP_MEMORY_TAGS 1
57#define CONFIG_INITRD_TAG 1
58#define CONFIG_REVISION_TAG 1
59
60/* Size of malloc() pool */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040061#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020062 /* Sector */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040063#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020064#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
65 /* initial data */
66
67/* Hardware drivers */
68
69/* DM9000 */
70#define CONFIG_NET_MULTI 1
71#define CONFIG_NET_RETRY_COUNT 20
72#define CONFIG_DRIVER_DM9000 1
73#define CONFIG_DM9000_BASE 0x2c000000
74#define DM9000_IO CONFIG_DM9000_BASE
75#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
76#define CONFIG_DM9000_USE_16BIT 1
77#define CONFIG_DM9000_NO_SROM 1
78#undef CONFIG_DM9000_DEBUG
79
80/* NS16550 Configuration */
81#define CONFIG_SYS_NS16550
82#define CONFIG_SYS_NS16550_SERIAL
83#define CONFIG_SYS_NS16550_REG_SIZE (-4)
84#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
85
86/* select serial console configuration */
87#define CONFIG_CONS_INDEX 3
88#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
89#define CONFIG_SERIAL3 3
90#define CONFIG_BAUDRATE 115200
91#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
92 115200}
93
94/* MMC */
95#define CONFIG_MMC 1
96#define CONFIG_OMAP3_MMC 1
97#define CONFIG_DOS_PARTITION 1
98
99/* I2C */
Tom Rix0297ec72009-09-29 10:19:49 -0400100#define CONFIG_HARD_I2C 1
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200101#define CONFIG_SYS_I2C_SPEED 100000
102#define CONFIG_SYS_I2C_SLAVE 1
103#define CONFIG_SYS_I2C_BUS 0
104#define CONFIG_SYS_I2C_BUS_SELECT 1
105#define CONFIG_DRIVER_OMAP34XX_I2C 1
106
107/* TWL4030 */
108#define CONFIG_TWL4030_POWER 1
109#define CONFIG_TWL4030_LED 1
110
111/* Board NAND Info */
112#define CONFIG_SYS_NO_FLASH /* no NOR flash */
113#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
114#define MTDIDS_DEFAULT "nand0=nand"
115#define MTDPARTS_DEFAULT "mtdparts=nand:" \
116 "512k(x-loader)," \
117 "1920k(u-boot)," \
118 "128k(u-boot-env)," \
119 "4m(kernel)," \
120 "-(fs)"
121
122#define CONFIG_NAND_OMAP_GPMC
123#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
124 /* to access nand */
125#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
126 /* to access nand at */
127 /* CS0 */
128#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
129
130#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
131 /* devices */
132#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
133
134#define CONFIG_JFFS2_NAND
135/* nand device jffs2 lives on */
136#define CONFIG_JFFS2_DEV "nand0"
137/* start of jffs2 partition */
138#define CONFIG_JFFS2_PART_OFFSET 0x680000
139#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
140 /* partition */
141
142/* commands to include */
143#include <config_cmd_default.h>
144
145#define CONFIG_CMD_DHCP /* DHCP support */
146#define CONFIG_CMD_EXT2 /* EXT2 Support */
147#define CONFIG_CMD_FAT /* FAT support */
148#define CONFIG_CMD_I2C /* I2C serial bus support */
149#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
150#define CONFIG_CMD_MMC /* MMC support */
151#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
152#define CONFIG_CMD_NAND /* NAND support */
153#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
154
155#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
156#undef CONFIG_CMD_IMI /* iminfo */
157
158/* BOOTP/DHCP options */
159#define CONFIG_BOOTP_SUBNETMASK
160#define CONFIG_BOOTP_GATEWAY
161#define CONFIG_BOOTP_HOSTNAME
162#define CONFIG_BOOTP_NISDOMAIN
163#define CONFIG_BOOTP_BOOTPATH
164#define CONFIG_BOOTP_BOOTFILESIZE
165#define CONFIG_BOOTP_DNS
166#define CONFIG_BOOTP_DNS2
167#define CONFIG_BOOTP_SEND_HOSTNAME
168#define CONFIG_BOOTP_NTPSERVER
169#define CONFIG_BOOTP_TIMEOFFSET
170#undef CONFIG_BOOTP_VENDOREX
171
172/* Environment information */
173#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
174
175#define CONFIG_BOOTDELAY 3
176
177#define CONFIG_EXTRA_ENV_SETTINGS \
178 "loadaddr=0x82000000\0" \
179 "console=ttyS2,115200n8\0" \
180 "vram=12M\0" \
181 "dvimode=1024x768MR-16@60\0" \
182 "defaultdisplay=dvi\0" \
183 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
184 "kernelopts=rw\0" \
185 "commonargs=" \
186 "setenv bootargs console=${console} " \
187 "vram=${vram} " \
188 "omapfb.mode=dvi:${dvimode} " \
189 "omapdss.def_disp=${defaultdisplay}\0" \
190 "mmcargs=" \
191 "run commonargs; " \
192 "setenv bootargs ${bootargs} " \
193 "root=/dev/mmcblk0p2 " \
194 "${kernelopts}\0" \
195 "nandargs=" \
196 "run commonargs; " \
197 "setenv bootargs ${bootargs} " \
198 "omapfb.mode=dvi:${dvimode} " \
199 "omapdss.def_disp=${defaultdisplay} " \
200 "root=/dev/mtdblock4 " \
201 "rootfstype=jffs2 " \
202 "${kernelopts}\0" \
203 "netargs=" \
204 "run commonargs; " \
205 "setenv bootargs ${bootargs} " \
206 "root=/dev/nfs " \
207 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
208 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
209 "${kernelopts} " \
210 "dnsip1=${dnsip} " \
211 "dnsip2=${dnsip2}\0" \
212 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
213 "bootscript=echo Running bootscript from mmc ...; " \
214 "source ${loadaddr}\0" \
215 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
216 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
217 "mmcboot=echo Booting from mmc ...; " \
218 "run mmcargs; " \
219 "bootm ${loadaddr}\0" \
220 "nandboot=echo Booting from nand ...; " \
221 "run nandargs; " \
222 "nand read ${loadaddr} 280000 400000; " \
223 "bootm ${loadaddr}\0" \
224 "netboot=echo Booting from network ...; " \
225 "dhcp ${loadaddr}; " \
226 "run netargs; " \
227 "bootm ${loadaddr}\0" \
228 "autoboot=if mmc init 0; then " \
229 "if run loadbootscript; then " \
230 "run bootscript; " \
231 "else " \
232 "if run loaduimage; then " \
233 "run mmcboot; " \
234 "else run nandboot; " \
235 "fi; " \
236 "fi; " \
237 "else run nandboot; fi\0"
238
239
240#define CONFIG_BOOTCOMMAND "run autoboot"
241
242/* Miscellaneous configurable options */
243#define CONFIG_SYS_LONGHELP /* undef to save memory */
244#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
245#define CONFIG_AUTO_COMPLETE 1
246#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
247#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
248#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
249/* Print Buffer Size */
250#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
251 sizeof(CONFIG_SYS_PROMPT) + 16)
252#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
253
254/* Boot Argument Buffer Size */
255#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
256
257#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
258#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
259 0x01000000) /* 16MB */
260
261#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
262
263/*
264 * OMAP3 has 12 GP timers, they can be driven by the system clock
265 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
266 * This rate is divided by a local divisor.
267 */
268#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
269#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
270#define CONFIG_SYS_HZ 1000
271
272/* The stack sizes are set up in start.S using the settings below */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400273#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200274#ifdef CONFIG_USE_IRQ
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400275#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
276#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200277#endif
278
279/* Physical Memory Map */
280#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
281#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400282#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200283#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
284
285/* SDRAM Bank Allocation method */
286#define SDRC_R_B_C 1
287
288/* NAND and environment organization */
289#define PISMO1_NAND_SIZE GPMC_SIZE_128M
290
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400291#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200292
293#define CONFIG_ENV_IS_IN_NAND 1
294#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
295
296#define CONFIG_ENV_OFFSET boot_flash_off
297
298#ifndef __ASSEMBLY__
299extern struct gpmc *gpmc_cfg;
300extern unsigned int boot_flash_base;
301extern volatile unsigned int boot_flash_env_addr;
302extern unsigned int boot_flash_off;
303extern unsigned int boot_flash_sec;
304extern unsigned int boot_flash_type;
305#endif
306
307#endif /* __CONFIG_H */