blob: 88e335836d7c48cd4e0333d61989383dff81e7af [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
3choice
4 prompt "Sunxi SoC Variant"
5
Ian Campbellc3be2792014-10-24 21:20:45 +01006config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +01007 bool "sun4i (Allwinner A10)"
8 select CPU_V7
9 select SUPPORT_SPL
10
Ian Campbellc3be2792014-10-24 21:20:45 +010011config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010012 bool "sun5i (Allwinner A13)"
13 select CPU_V7
14 select SUPPORT_SPL
15
Ian Campbellc3be2792014-10-24 21:20:45 +010016config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010017 bool "sun6i (Allwinner A31)"
18 select CPU_V7
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020019 select SUPPORT_SPL
Ian Campbell2c7e3b92014-10-24 21:20:44 +010020
Ian Campbellc3be2792014-10-24 21:20:45 +010021config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010022 bool "sun7i (Allwinner A20)"
23 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010024 select CPU_V7_HAS_NONSEC
25 select CPU_V7_HAS_VIRT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010026 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020027 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010028
Ian Campbellc3be2792014-10-24 21:20:45 +010029config MACH_SUN8I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010030 bool "sun8i (Allwinner A23)"
31 select CPU_V7
Hans de Goede08fd1472014-12-07 14:34:27 +010032 select SUPPORT_SPL
Ian Campbell2c7e3b92014-10-24 21:20:44 +010033
34endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +080035
Hans de Goede37781a12014-11-15 19:46:39 +010036config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +010037 int "sunxi dram clock speed"
38 default 312 if MACH_SUN6I || MACH_SUN8I
39 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010040 ---help---
41 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +010042 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +010043
Siarhei Siamashka47e35012015-02-01 00:27:06 +020044if MACH_SUN5I || MACH_SUN7I
45config DRAM_MBUS_CLK
46 int "sunxi mbus clock speed"
47 default 300
48 ---help---
49 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
50
51endif
52
Hans de Goede37781a12014-11-15 19:46:39 +010053config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +010054 int "sunxi dram zq value"
55 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
56 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010057 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +010058 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +010059
Hans de Goede8ffc4872015-01-17 14:24:55 +010060if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
61config DRAM_EMR1
62 int "sunxi dram emr1 value"
63 default 0 if MACH_SUN4I
64 default 4 if MACH_SUN5I || MACH_SUN7I
65 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +010066 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +020067
Siarhei Siamashka47e35012015-02-01 00:27:06 +020068config DRAM_ODT_EN
69 int "sunxi dram odt_en value"
70 default 0
71 ---help---
72 Set the dram controller odt_en parameter. This can be used to
73 enable/disable the ODT feature.
74
75config DRAM_TPR3
76 hex "sunxi dram tpr3 value"
77 default 0
78 ---help---
79 Set the dram controller tpr3 parameter. This parameter configures
80 the delay on the command lane and also phase shifts, which are
81 applied for sampling incoming read data. The default value 0
82 means that no phase/delay adjustments are necessary. Properly
83 configuring this parameter increases reliability at high DRAM
84 clock speeds.
85
86config DRAM_DQS_GATING_DELAY
87 hex "sunxi dram dqs_gating_delay value"
88 default 0
89 ---help---
90 Set the dram controller dqs_gating_delay parmeter. Each byte
91 encodes the DQS gating delay for each byte lane. The delay
92 granularity is 1/4 cycle. For example, the value 0x05060606
93 means that the delay is 5 quarter-cycles for one lane (1.25
94 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
95 The default value 0 means autodetection. The results of hardware
96 autodetection are not very reliable and depend on the chip
97 temperature (sometimes producing different results on cold start
98 and warm reboot). But the accuracy of hardware autodetection
99 is usually good enough, unless running at really high DRAM
100 clocks speeds (up to 600MHz). If unsure, keep as 0.
101
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200102choice
103 prompt "sunxi dram timings"
104 default DRAM_TIMINGS_VENDOR_MAGIC
105 ---help---
106 Select the timings of the DDR3 chips.
107
108config DRAM_TIMINGS_VENDOR_MAGIC
109 bool "Magic vendor timings from Android"
110 ---help---
111 The same DRAM timings as in the Allwinner boot0 bootloader.
112
113config DRAM_TIMINGS_DDR3_1066F_1333H
114 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
115 ---help---
116 Use the timings of the standard JEDEC DDR3-1066F speed bin for
117 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
118 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
119 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
120 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
121 that down binning to DDR3-1066F is supported (because DDR3-1066F
122 uses a bit faster timings than DDR3-1333H).
123
124config DRAM_TIMINGS_DDR3_800E_1066G_1333J
125 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
126 ---help---
127 Use the timings of the slowest possible JEDEC speed bin for the
128 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
129 DDR3-800E, DDR3-1066G or DDR3-1333J.
130
131endchoice
132
Hans de Goede37781a12014-11-15 19:46:39 +0100133endif
134
Iain Patone71b4222015-03-28 10:26:38 +0000135config SYS_CLK_FREQ
136 default 912000000 if MACH_SUN7I
137 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
138
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800139config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100140 default "sun4i" if MACH_SUN4I
141 default "sun5i" if MACH_SUN5I
142 default "sun6i" if MACH_SUN6I
143 default "sun7i" if MACH_SUN7I
144 default "sun8i" if MACH_SUN8I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200145
Masahiro Yamadadd840582014-07-30 14:08:14 +0900146config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900147 default "sunxi"
148
149config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900150 default "sunxi"
151
Ian Campbell4ce99412014-10-24 21:20:46 +0100152config SPL_FEL
153 bool "SPL/FEL mode support"
154 depends on SPL
155 default n
Simon Glass942cb0b2015-02-07 10:47:30 -0700156 help
157 This enables support for Fast Early Loader (FEL) mode. This
158 allows U-Boot to be loaded to the board over USB by the on-chip
159 boot rom. U-Boot should be sent in two parts: SPL first, with
160 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with
161 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option
162 shrinks the amount of SRAM available to SPL, so only enable it if
163 you need FEL. Note that enabling this option only allows FEL to be
164 used; it is still possible to boot U-Boot from boot media. U-Boot
165 SPL detects when it is being loaded using FEL.
Ian Campbell4ce99412014-10-24 21:20:46 +0100166
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200167config UART0_PORT_F
168 bool "UART0 on MicroSD breakout board"
169 depends on SPL_FEL
170 default n
171 ---help---
172 Repurpose the SD card slot for getting access to the UART0 serial
173 console. Primarily useful only for low level u-boot debugging on
174 tablets, where normal UART0 is difficult to access and requires
175 device disassembly and/or soldering. As the SD card can't be used
176 at the same time, the system can be only booted in the FEL mode.
177 Only enable this if you really know what you are doing.
178
Ian Campbell98e214d2014-08-31 13:13:43 +0100179config FDTFILE
180 string "Default fdtfile env setting for this board"
Hans de Goede846e3252014-08-01 09:37:58 +0200181
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200182config OLD_SUNXI_KERNEL_COMPAT
183 boolean "Enable workarounds for booting old kernels"
184 default n
185 ---help---
186 Set this to enable various workarounds for old kernels, this results in
187 sub-optimal settings for newer kernels, only enable if needed.
188
Hans de Goedecd821132014-10-02 20:29:26 +0200189config MMC0_CD_PIN
190 string "Card detect pin for mmc0"
191 default ""
192 ---help---
193 Set the card detect pin for mmc0, leave empty to not use cd. This
194 takes a string in the format understood by sunxi_name_to_gpio, e.g.
195 PH1 for pin 1 of port H.
196
197config MMC1_CD_PIN
198 string "Card detect pin for mmc1"
199 default ""
200 ---help---
201 See MMC0_CD_PIN help text.
202
203config MMC2_CD_PIN
204 string "Card detect pin for mmc2"
205 default ""
206 ---help---
207 See MMC0_CD_PIN help text.
208
209config MMC3_CD_PIN
210 string "Card detect pin for mmc3"
211 default ""
212 ---help---
213 See MMC0_CD_PIN help text.
214
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100215config MMC1_PINS
216 string "Pins for mmc1"
217 default ""
218 ---help---
219 Set the pins used for mmc1, when applicable. This takes a string in the
220 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
221
222config MMC2_PINS
223 string "Pins for mmc2"
224 default ""
225 ---help---
226 See MMC1_PINS help text.
227
228config MMC3_PINS
229 string "Pins for mmc3"
230 default ""
231 ---help---
232 See MMC1_PINS help text.
233
Hans de Goede2ccfac02014-10-02 20:43:50 +0200234config MMC_SUNXI_SLOT_EXTRA
235 int "mmc extra slot number"
236 default -1
237 ---help---
238 sunxi builds always enable mmc0, some boards also have a second sdcard
239 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
240 support for this.
241
Hans de Goede4458b7a2015-01-07 15:26:06 +0100242config USB0_VBUS_PIN
243 string "Vbus enable pin for usb0 (otg)"
244 default ""
245 ---help---
246 Set the Vbus enable pin for usb0 (otg). This takes a string in the
247 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
248
Hans de Goede52defe82015-02-16 22:13:43 +0100249config USB0_VBUS_DET
250 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100251 default ""
252 ---help---
253 Set the Vbus detect pin for usb0 (otg). This takes a string in the
254 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
255
Hans de Goede115200c2014-11-07 16:09:00 +0100256config USB1_VBUS_PIN
257 string "Vbus enable pin for usb1 (ehci0)"
258 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100259 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100260 ---help---
261 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
262 a string in the format understood by sunxi_name_to_gpio, e.g.
263 PH1 for pin 1 of port H.
264
265config USB2_VBUS_PIN
266 string "Vbus enable pin for usb2 (ehci1)"
267 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100268 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100269 ---help---
270 See USB1_VBUS_PIN help text.
271
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200272config I2C0_ENABLE
273 bool "Enable I2C/TWI controller 0"
274 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
275 default n if MACH_SUN6I || MACH_SUN8I
276 ---help---
277 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
278 its clock and setting up the bus. This is especially useful on devices
279 with slaves connected to the bus or with pins exposed through e.g. an
280 expansion port/header.
281
282config I2C1_ENABLE
283 bool "Enable I2C/TWI controller 1"
284 default n
285 ---help---
286 See I2C0_ENABLE help text.
287
288config I2C2_ENABLE
289 bool "Enable I2C/TWI controller 2"
290 default n
291 ---help---
292 See I2C0_ENABLE help text.
293
294if MACH_SUN6I || MACH_SUN7I
295config I2C3_ENABLE
296 bool "Enable I2C/TWI controller 3"
297 default n
298 ---help---
299 See I2C0_ENABLE help text.
300endif
301
302if MACH_SUN7I
303config I2C4_ENABLE
304 bool "Enable I2C/TWI controller 4"
305 default n
306 ---help---
307 See I2C0_ENABLE help text.
308endif
309
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200310config VIDEO
Hans de Goede2dae8002014-12-21 16:28:32 +0100311 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200312 default y
313 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100314 Say Y here to add support for using a cfb console on the HDMI, LCD
315 or VGA output found on most sunxi devices. See doc/README.video for
316 info on how to select the video output and mode.
317
Hans de Goede2fbf0912014-12-23 23:04:35 +0100318config VIDEO_HDMI
319 boolean "HDMI output support"
320 depends on VIDEO && !MACH_SUN8I
321 default y
322 ---help---
323 Say Y here to add support for outputting video over HDMI.
324
Hans de Goeded9786d22014-12-25 13:58:06 +0100325config VIDEO_VGA
326 boolean "VGA output support"
327 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
328 default n
329 ---help---
330 Say Y here to add support for outputting video over VGA.
331
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100332config VIDEO_VGA_VIA_LCD
333 boolean "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800334 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100335 default n
336 ---help---
337 Say Y here to add support for external DACs connected to the parallel
338 LCD interface driving a VGA connector, such as found on the
339 Olimex A13 boards.
340
Hans de Goedefb75d972015-01-25 15:33:07 +0100341config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
342 boolean "Force sync active high for VGA via LCD controller support"
343 depends on VIDEO_VGA_VIA_LCD
344 default n
345 ---help---
346 Say Y here if you've a board which uses opendrain drivers for the vga
347 hsync and vsync signals. Opendrain drivers cannot generate steep enough
348 positive edges for a stable video output, so on boards with opendrain
349 drivers the sync signals must always be active high.
350
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800351config VIDEO_VGA_EXTERNAL_DAC_EN
352 string "LCD panel power enable pin"
353 depends on VIDEO_VGA_VIA_LCD
354 default ""
355 ---help---
356 Set the enable pin for the external VGA DAC. This takes a string in the
357 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
358
Hans de Goede2dae8002014-12-21 16:28:32 +0100359config VIDEO_LCD_MODE
360 string "LCD panel timing details"
361 depends on VIDEO
362 default ""
363 ---help---
364 LCD panel timing details string, leave empty if there is no LCD panel.
365 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
366 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
367
Hans de Goede65150322015-01-13 13:21:46 +0100368config VIDEO_LCD_DCLK_PHASE
369 int "LCD panel display clock phase"
370 depends on VIDEO
371 default 1
372 ---help---
373 Select LCD panel display clock phase shift, range 0-3.
374
Hans de Goede2dae8002014-12-21 16:28:32 +0100375config VIDEO_LCD_POWER
376 string "LCD panel power enable pin"
377 depends on VIDEO
378 default ""
379 ---help---
380 Set the power enable pin for the LCD panel. This takes a string in the
381 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
382
Hans de Goede242e3d82015-02-16 17:26:41 +0100383config VIDEO_LCD_RESET
384 string "LCD panel reset pin"
385 depends on VIDEO
386 default ""
387 ---help---
388 Set the reset pin for the LCD panel. This takes a string in the format
389 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
390
Hans de Goede2dae8002014-12-21 16:28:32 +0100391config VIDEO_LCD_BL_EN
392 string "LCD panel backlight enable pin"
393 depends on VIDEO
394 default ""
395 ---help---
396 Set the backlight enable pin for the LCD panel. This takes a string in the
397 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
398 port H.
399
400config VIDEO_LCD_BL_PWM
401 string "LCD panel backlight pwm pin"
402 depends on VIDEO
403 default ""
404 ---help---
405 Set the backlight pwm pin for the LCD panel. This takes a string in the
406 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200407
Hans de Goedea7403ae2015-01-22 21:02:42 +0100408config VIDEO_LCD_BL_PWM_ACTIVE_LOW
409 bool "LCD panel backlight pwm is inverted"
410 depends on VIDEO
411 default y
412 ---help---
413 Set this if the backlight pwm output is active low.
414
Hans de Goede55410082015-02-16 17:23:25 +0100415config VIDEO_LCD_PANEL_I2C
416 bool "LCD panel needs to be configured via i2c"
417 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100418 default n
Hans de Goede55410082015-02-16 17:23:25 +0100419 ---help---
420 Say y here if the LCD panel needs to be configured via i2c. This
421 will add a bitbang i2c controller using gpios to talk to the LCD.
422
423config VIDEO_LCD_PANEL_I2C_SDA
424 string "LCD panel i2c interface SDA pin"
425 depends on VIDEO_LCD_PANEL_I2C
426 default "PG12"
427 ---help---
428 Set the SDA pin for the LCD i2c interface. This takes a string in the
429 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
430
431config VIDEO_LCD_PANEL_I2C_SCL
432 string "LCD panel i2c interface SCL pin"
433 depends on VIDEO_LCD_PANEL_I2C
434 default "PG10"
435 ---help---
436 Set the SCL pin for the LCD i2c interface. This takes a string in the
437 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
438
Hans de Goede213480e2015-01-01 22:04:34 +0100439
440# Note only one of these may be selected at a time! But hidden choices are
441# not supported by Kconfig
442config VIDEO_LCD_IF_PARALLEL
443 bool
444
445config VIDEO_LCD_IF_LVDS
446 bool
447
448
449choice
450 prompt "LCD panel support"
451 depends on VIDEO
452 ---help---
453 Select which type of LCD panel to support.
454
455config VIDEO_LCD_PANEL_PARALLEL
456 bool "Generic parallel interface LCD panel"
457 select VIDEO_LCD_IF_PARALLEL
458
459config VIDEO_LCD_PANEL_LVDS
460 bool "Generic lvds interface LCD panel"
461 select VIDEO_LCD_IF_LVDS
462
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200463config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
464 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
465 select VIDEO_LCD_SSD2828
466 select VIDEO_LCD_IF_PARALLEL
467 ---help---
468 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
469
Hans de Goede27515b22015-01-20 09:23:36 +0100470config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
471 bool "Hitachi tx18d42vm LCD panel"
472 select VIDEO_LCD_HITACHI_TX18D42VM
473 select VIDEO_LCD_IF_LVDS
474 ---help---
475 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
476
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100477config VIDEO_LCD_TL059WV5C0
478 bool "tl059wv5c0 LCD panel"
479 select VIDEO_LCD_PANEL_I2C
480 select VIDEO_LCD_IF_PARALLEL
481 ---help---
482 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
483 Aigo M60/M608/M606 tablets.
484
Hans de Goede213480e2015-01-01 22:04:34 +0100485endchoice
486
487
Hans de Goede1a800f72015-01-11 17:17:00 +0100488config USB_MUSB_SUNXI
489 bool "Enable sunxi OTG / DRC USB controller in host mode"
490 default n
491 ---help---
492 Say y here to enable support for the sunxi OTG / DRC USB controller
493 used on almost all sunxi boards. Note currently u-boot can only have
494 one usb host controller enabled at a time, so enabling this on boards
495 which also use the ehci host controller will result in build errors.
496
Hans de Goede86b49092014-09-18 21:03:34 +0200497config USB_KEYBOARD
498 boolean "Enable USB keyboard support"
499 default y
500 ---help---
501 Say Y here to add support for using a USB keyboard (typically used
Hans de Goede2dae8002014-12-21 16:28:32 +0100502 in combination with a graphical console).
Hans de Goede86b49092014-09-18 21:03:34 +0200503
Hans de Goedec13f60d2015-01-25 12:10:48 +0100504config GMAC_TX_DELAY
505 int "GMAC Transmit Clock Delay Chain"
506 default 0
507 ---help---
508 Set the GMAC Transmit Clock Delay Chain value.
509
Masahiro Yamadadd840582014-07-30 14:08:14 +0900510endif