Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 1 | if ARCH_SUNXI |
| 2 | |
| 3 | choice |
| 4 | prompt "Sunxi SoC Variant" |
| 5 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 6 | config MACH_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 7 | bool "sun4i (Allwinner A10)" |
| 8 | select CPU_V7 |
| 9 | select SUPPORT_SPL |
| 10 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 11 | config MACH_SUN5I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 12 | bool "sun5i (Allwinner A13)" |
| 13 | select CPU_V7 |
| 14 | select SUPPORT_SPL |
| 15 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 16 | config MACH_SUN6I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 17 | bool "sun6i (Allwinner A31)" |
| 18 | select CPU_V7 |
Hans de Goede | 8c2c9cf | 2014-10-25 20:18:10 +0200 | [diff] [blame] | 19 | select SUPPORT_SPL |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 20 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 21 | config MACH_SUN7I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 22 | bool "sun7i (Allwinner A20)" |
| 23 | select CPU_V7 |
Hans de Goede | ea624e1 | 2014-11-14 09:34:30 +0100 | [diff] [blame] | 24 | select CPU_V7_HAS_NONSEC |
| 25 | select CPU_V7_HAS_VIRT |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 26 | select SUPPORT_SPL |
Hans de Goede | b366fb9 | 2014-10-24 20:12:04 +0200 | [diff] [blame] | 27 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 28 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 29 | config MACH_SUN8I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 30 | bool "sun8i (Allwinner A23)" |
| 31 | select CPU_V7 |
Hans de Goede | 08fd147 | 2014-12-07 14:34:27 +0100 | [diff] [blame] | 32 | select SUPPORT_SPL |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 33 | |
| 34 | endchoice |
Maxime Ripard | 8a6564d | 2014-10-03 20:16:29 +0800 | [diff] [blame] | 35 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 36 | config DRAM_CLK |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 37 | int "sunxi dram clock speed" |
| 38 | default 312 if MACH_SUN6I || MACH_SUN8I |
| 39 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 40 | ---help--- |
| 41 | Set the dram clock speed, valid range 240 - 480, must be a multiple |
Hans de Goede | e1a0888 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 42 | of 24. |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 43 | |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 44 | if MACH_SUN5I || MACH_SUN7I |
| 45 | config DRAM_MBUS_CLK |
| 46 | int "sunxi mbus clock speed" |
| 47 | default 300 |
| 48 | ---help--- |
| 49 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. |
| 50 | |
| 51 | endif |
| 52 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 53 | config DRAM_ZQ |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 54 | int "sunxi dram zq value" |
| 55 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I |
| 56 | default 127 if MACH_SUN7I |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 57 | ---help--- |
Hans de Goede | e1a0888 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 58 | Set the dram zq value. |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 59 | |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 60 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
| 61 | config DRAM_EMR1 |
| 62 | int "sunxi dram emr1 value" |
| 63 | default 0 if MACH_SUN4I |
| 64 | default 4 if MACH_SUN5I || MACH_SUN7I |
| 65 | ---help--- |
Hans de Goede | e1a0888 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 66 | Set the dram controller emr1 value. |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 67 | |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 68 | config DRAM_ODT_EN |
| 69 | int "sunxi dram odt_en value" |
| 70 | default 0 |
| 71 | ---help--- |
| 72 | Set the dram controller odt_en parameter. This can be used to |
| 73 | enable/disable the ODT feature. |
| 74 | |
| 75 | config DRAM_TPR3 |
| 76 | hex "sunxi dram tpr3 value" |
| 77 | default 0 |
| 78 | ---help--- |
| 79 | Set the dram controller tpr3 parameter. This parameter configures |
| 80 | the delay on the command lane and also phase shifts, which are |
| 81 | applied for sampling incoming read data. The default value 0 |
| 82 | means that no phase/delay adjustments are necessary. Properly |
| 83 | configuring this parameter increases reliability at high DRAM |
| 84 | clock speeds. |
| 85 | |
| 86 | config DRAM_DQS_GATING_DELAY |
| 87 | hex "sunxi dram dqs_gating_delay value" |
| 88 | default 0 |
| 89 | ---help--- |
| 90 | Set the dram controller dqs_gating_delay parmeter. Each byte |
| 91 | encodes the DQS gating delay for each byte lane. The delay |
| 92 | granularity is 1/4 cycle. For example, the value 0x05060606 |
| 93 | means that the delay is 5 quarter-cycles for one lane (1.25 |
| 94 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. |
| 95 | The default value 0 means autodetection. The results of hardware |
| 96 | autodetection are not very reliable and depend on the chip |
| 97 | temperature (sometimes producing different results on cold start |
| 98 | and warm reboot). But the accuracy of hardware autodetection |
| 99 | is usually good enough, unless running at really high DRAM |
| 100 | clocks speeds (up to 600MHz). If unsure, keep as 0. |
| 101 | |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 102 | choice |
| 103 | prompt "sunxi dram timings" |
| 104 | default DRAM_TIMINGS_VENDOR_MAGIC |
| 105 | ---help--- |
| 106 | Select the timings of the DDR3 chips. |
| 107 | |
| 108 | config DRAM_TIMINGS_VENDOR_MAGIC |
| 109 | bool "Magic vendor timings from Android" |
| 110 | ---help--- |
| 111 | The same DRAM timings as in the Allwinner boot0 bootloader. |
| 112 | |
| 113 | config DRAM_TIMINGS_DDR3_1066F_1333H |
| 114 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" |
| 115 | ---help--- |
| 116 | Use the timings of the standard JEDEC DDR3-1066F speed bin for |
| 117 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin |
| 118 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips |
| 119 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 |
| 120 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm |
| 121 | that down binning to DDR3-1066F is supported (because DDR3-1066F |
| 122 | uses a bit faster timings than DDR3-1333H). |
| 123 | |
| 124 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J |
| 125 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" |
| 126 | ---help--- |
| 127 | Use the timings of the slowest possible JEDEC speed bin for the |
| 128 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be |
| 129 | DDR3-800E, DDR3-1066G or DDR3-1333J. |
| 130 | |
| 131 | endchoice |
| 132 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 133 | endif |
| 134 | |
Maxime Ripard | 8a6564d | 2014-10-03 20:16:29 +0800 | [diff] [blame] | 135 | config SYS_CONFIG_NAME |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 136 | default "sun4i" if MACH_SUN4I |
| 137 | default "sun5i" if MACH_SUN5I |
| 138 | default "sun6i" if MACH_SUN6I |
| 139 | default "sun7i" if MACH_SUN7I |
| 140 | default "sun8i" if MACH_SUN8I |
Hans de Goede | 6ae66f2 | 2014-08-01 09:28:24 +0200 | [diff] [blame] | 141 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 142 | config SYS_BOARD |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 143 | default "sunxi" |
| 144 | |
| 145 | config SYS_SOC |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 146 | default "sunxi" |
| 147 | |
Ian Campbell | 4ce9941 | 2014-10-24 21:20:46 +0100 | [diff] [blame] | 148 | config SPL_FEL |
| 149 | bool "SPL/FEL mode support" |
| 150 | depends on SPL |
| 151 | default n |
Simon Glass | 942cb0b | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 152 | help |
| 153 | This enables support for Fast Early Loader (FEL) mode. This |
| 154 | allows U-Boot to be loaded to the board over USB by the on-chip |
| 155 | boot rom. U-Boot should be sent in two parts: SPL first, with |
| 156 | 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with |
| 157 | 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option |
| 158 | shrinks the amount of SRAM available to SPL, so only enable it if |
| 159 | you need FEL. Note that enabling this option only allows FEL to be |
| 160 | used; it is still possible to boot U-Boot from boot media. U-Boot |
| 161 | SPL detects when it is being loaded using FEL. |
Ian Campbell | 4ce9941 | 2014-10-24 21:20:46 +0100 | [diff] [blame] | 162 | |
Siarhei Siamashka | f0ce28e | 2014-12-25 02:34:47 +0200 | [diff] [blame] | 163 | config UART0_PORT_F |
| 164 | bool "UART0 on MicroSD breakout board" |
| 165 | depends on SPL_FEL |
| 166 | default n |
| 167 | ---help--- |
| 168 | Repurpose the SD card slot for getting access to the UART0 serial |
| 169 | console. Primarily useful only for low level u-boot debugging on |
| 170 | tablets, where normal UART0 is difficult to access and requires |
| 171 | device disassembly and/or soldering. As the SD card can't be used |
| 172 | at the same time, the system can be only booted in the FEL mode. |
| 173 | Only enable this if you really know what you are doing. |
| 174 | |
Ian Campbell | 98e214d | 2014-08-31 13:13:43 +0100 | [diff] [blame] | 175 | config FDTFILE |
| 176 | string "Default fdtfile env setting for this board" |
Hans de Goede | 846e325 | 2014-08-01 09:37:58 +0200 | [diff] [blame] | 177 | |
Hans de Goede | accc9e4 | 2014-10-22 14:56:36 +0200 | [diff] [blame] | 178 | config OLD_SUNXI_KERNEL_COMPAT |
| 179 | boolean "Enable workarounds for booting old kernels" |
| 180 | default n |
| 181 | ---help--- |
| 182 | Set this to enable various workarounds for old kernels, this results in |
| 183 | sub-optimal settings for newer kernels, only enable if needed. |
| 184 | |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 185 | config MMC0_CD_PIN |
| 186 | string "Card detect pin for mmc0" |
| 187 | default "" |
| 188 | ---help--- |
| 189 | Set the card detect pin for mmc0, leave empty to not use cd. This |
| 190 | takes a string in the format understood by sunxi_name_to_gpio, e.g. |
| 191 | PH1 for pin 1 of port H. |
| 192 | |
| 193 | config MMC1_CD_PIN |
| 194 | string "Card detect pin for mmc1" |
| 195 | default "" |
| 196 | ---help--- |
| 197 | See MMC0_CD_PIN help text. |
| 198 | |
| 199 | config MMC2_CD_PIN |
| 200 | string "Card detect pin for mmc2" |
| 201 | default "" |
| 202 | ---help--- |
| 203 | See MMC0_CD_PIN help text. |
| 204 | |
| 205 | config MMC3_CD_PIN |
| 206 | string "Card detect pin for mmc3" |
| 207 | default "" |
| 208 | ---help--- |
| 209 | See MMC0_CD_PIN help text. |
| 210 | |
Hans de Goede | 2ccfac0 | 2014-10-02 20:43:50 +0200 | [diff] [blame] | 211 | config MMC_SUNXI_SLOT_EXTRA |
| 212 | int "mmc extra slot number" |
| 213 | default -1 |
| 214 | ---help--- |
| 215 | sunxi builds always enable mmc0, some boards also have a second sdcard |
| 216 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable |
| 217 | support for this. |
| 218 | |
Hans de Goede | 4458b7a | 2015-01-07 15:26:06 +0100 | [diff] [blame] | 219 | config USB0_VBUS_PIN |
| 220 | string "Vbus enable pin for usb0 (otg)" |
| 221 | default "" |
| 222 | ---help--- |
| 223 | Set the Vbus enable pin for usb0 (otg). This takes a string in the |
| 224 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 225 | |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 226 | config USB1_VBUS_PIN |
| 227 | string "Vbus enable pin for usb1 (ehci0)" |
| 228 | default "PH6" if MACH_SUN4I || MACH_SUN7I |
Hans de Goede | 76946df | 2014-11-07 14:51:12 +0100 | [diff] [blame] | 229 | default "PH27" if MACH_SUN6I |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 230 | ---help--- |
| 231 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes |
| 232 | a string in the format understood by sunxi_name_to_gpio, e.g. |
| 233 | PH1 for pin 1 of port H. |
| 234 | |
| 235 | config USB2_VBUS_PIN |
| 236 | string "Vbus enable pin for usb2 (ehci1)" |
| 237 | default "PH3" if MACH_SUN4I || MACH_SUN7I |
Hans de Goede | 76946df | 2014-11-07 14:51:12 +0100 | [diff] [blame] | 238 | default "PH24" if MACH_SUN6I |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 239 | ---help--- |
| 240 | See USB1_VBUS_PIN help text. |
| 241 | |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 242 | config VIDEO |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 243 | boolean "Enable graphical uboot console on HDMI, LCD or VGA" |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 244 | default y |
| 245 | ---help--- |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 246 | Say Y here to add support for using a cfb console on the HDMI, LCD |
| 247 | or VGA output found on most sunxi devices. See doc/README.video for |
| 248 | info on how to select the video output and mode. |
| 249 | |
Hans de Goede | 2fbf091 | 2014-12-23 23:04:35 +0100 | [diff] [blame] | 250 | config VIDEO_HDMI |
| 251 | boolean "HDMI output support" |
| 252 | depends on VIDEO && !MACH_SUN8I |
| 253 | default y |
| 254 | ---help--- |
| 255 | Say Y here to add support for outputting video over HDMI. |
| 256 | |
Hans de Goede | d9786d2 | 2014-12-25 13:58:06 +0100 | [diff] [blame] | 257 | config VIDEO_VGA |
| 258 | boolean "VGA output support" |
| 259 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
| 260 | default n |
| 261 | ---help--- |
| 262 | Say Y here to add support for outputting video over VGA. |
| 263 | |
Hans de Goede | e2bbdfb | 2014-12-24 12:17:07 +0100 | [diff] [blame] | 264 | config VIDEO_VGA_VIA_LCD |
| 265 | boolean "VGA via LCD controller support" |
Chen-Yu Tsai | 2583d5b | 2015-01-12 18:02:10 +0800 | [diff] [blame] | 266 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
Hans de Goede | e2bbdfb | 2014-12-24 12:17:07 +0100 | [diff] [blame] | 267 | default n |
| 268 | ---help--- |
| 269 | Say Y here to add support for external DACs connected to the parallel |
| 270 | LCD interface driving a VGA connector, such as found on the |
| 271 | Olimex A13 boards. |
| 272 | |
Hans de Goede | fb75d97 | 2015-01-25 15:33:07 +0100 | [diff] [blame] | 273 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
| 274 | boolean "Force sync active high for VGA via LCD controller support" |
| 275 | depends on VIDEO_VGA_VIA_LCD |
| 276 | default n |
| 277 | ---help--- |
| 278 | Say Y here if you've a board which uses opendrain drivers for the vga |
| 279 | hsync and vsync signals. Opendrain drivers cannot generate steep enough |
| 280 | positive edges for a stable video output, so on boards with opendrain |
| 281 | drivers the sync signals must always be active high. |
| 282 | |
Chen-Yu Tsai | 507e27d | 2015-01-12 18:02:11 +0800 | [diff] [blame] | 283 | config VIDEO_VGA_EXTERNAL_DAC_EN |
| 284 | string "LCD panel power enable pin" |
| 285 | depends on VIDEO_VGA_VIA_LCD |
| 286 | default "" |
| 287 | ---help--- |
| 288 | Set the enable pin for the external VGA DAC. This takes a string in the |
| 289 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 290 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 291 | config VIDEO_LCD_MODE |
| 292 | string "LCD panel timing details" |
| 293 | depends on VIDEO |
| 294 | default "" |
| 295 | ---help--- |
| 296 | LCD panel timing details string, leave empty if there is no LCD panel. |
| 297 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. |
| 298 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 |
| 299 | |
Hans de Goede | 6515032 | 2015-01-13 13:21:46 +0100 | [diff] [blame] | 300 | config VIDEO_LCD_DCLK_PHASE |
| 301 | int "LCD panel display clock phase" |
| 302 | depends on VIDEO |
| 303 | default 1 |
| 304 | ---help--- |
| 305 | Select LCD panel display clock phase shift, range 0-3. |
| 306 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 307 | config VIDEO_LCD_POWER |
| 308 | string "LCD panel power enable pin" |
| 309 | depends on VIDEO |
| 310 | default "" |
| 311 | ---help--- |
| 312 | Set the power enable pin for the LCD panel. This takes a string in the |
| 313 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 314 | |
Hans de Goede | 242e3d8 | 2015-02-16 17:26:41 +0100 | [diff] [blame^] | 315 | config VIDEO_LCD_RESET |
| 316 | string "LCD panel reset pin" |
| 317 | depends on VIDEO |
| 318 | default "" |
| 319 | ---help--- |
| 320 | Set the reset pin for the LCD panel. This takes a string in the format |
| 321 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 322 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 323 | config VIDEO_LCD_BL_EN |
| 324 | string "LCD panel backlight enable pin" |
| 325 | depends on VIDEO |
| 326 | default "" |
| 327 | ---help--- |
| 328 | Set the backlight enable pin for the LCD panel. This takes a string in the |
| 329 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of |
| 330 | port H. |
| 331 | |
| 332 | config VIDEO_LCD_BL_PWM |
| 333 | string "LCD panel backlight pwm pin" |
| 334 | depends on VIDEO |
| 335 | default "" |
| 336 | ---help--- |
| 337 | Set the backlight pwm pin for the LCD panel. This takes a string in the |
| 338 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 339 | |
Hans de Goede | a7403ae | 2015-01-22 21:02:42 +0100 | [diff] [blame] | 340 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
| 341 | bool "LCD panel backlight pwm is inverted" |
| 342 | depends on VIDEO |
| 343 | default y |
| 344 | ---help--- |
| 345 | Set this if the backlight pwm output is active low. |
| 346 | |
Hans de Goede | 213480e | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 347 | |
| 348 | # Note only one of these may be selected at a time! But hidden choices are |
| 349 | # not supported by Kconfig |
| 350 | config VIDEO_LCD_IF_PARALLEL |
| 351 | bool |
| 352 | |
| 353 | config VIDEO_LCD_IF_LVDS |
| 354 | bool |
| 355 | |
| 356 | |
| 357 | choice |
| 358 | prompt "LCD panel support" |
| 359 | depends on VIDEO |
| 360 | ---help--- |
| 361 | Select which type of LCD panel to support. |
| 362 | |
| 363 | config VIDEO_LCD_PANEL_PARALLEL |
| 364 | bool "Generic parallel interface LCD panel" |
| 365 | select VIDEO_LCD_IF_PARALLEL |
| 366 | |
| 367 | config VIDEO_LCD_PANEL_LVDS |
| 368 | bool "Generic lvds interface LCD panel" |
| 369 | select VIDEO_LCD_IF_LVDS |
| 370 | |
Siarhei Siamashka | 97ece83 | 2015-01-19 05:23:33 +0200 | [diff] [blame] | 371 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
| 372 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" |
| 373 | select VIDEO_LCD_SSD2828 |
| 374 | select VIDEO_LCD_IF_PARALLEL |
| 375 | ---help--- |
| 376 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
| 377 | |
Hans de Goede | 27515b2 | 2015-01-20 09:23:36 +0100 | [diff] [blame] | 378 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
| 379 | bool "Hitachi tx18d42vm LCD panel" |
| 380 | select VIDEO_LCD_HITACHI_TX18D42VM |
| 381 | select VIDEO_LCD_IF_LVDS |
| 382 | ---help--- |
| 383 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support |
| 384 | |
Hans de Goede | 213480e | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 385 | endchoice |
| 386 | |
| 387 | |
Hans de Goede | 1a800f7 | 2015-01-11 17:17:00 +0100 | [diff] [blame] | 388 | config USB_MUSB_SUNXI |
| 389 | bool "Enable sunxi OTG / DRC USB controller in host mode" |
| 390 | default n |
| 391 | ---help--- |
| 392 | Say y here to enable support for the sunxi OTG / DRC USB controller |
| 393 | used on almost all sunxi boards. Note currently u-boot can only have |
| 394 | one usb host controller enabled at a time, so enabling this on boards |
| 395 | which also use the ehci host controller will result in build errors. |
| 396 | |
Hans de Goede | 86b4909 | 2014-09-18 21:03:34 +0200 | [diff] [blame] | 397 | config USB_KEYBOARD |
| 398 | boolean "Enable USB keyboard support" |
| 399 | default y |
| 400 | ---help--- |
| 401 | Say Y here to add support for using a USB keyboard (typically used |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 402 | in combination with a graphical console). |
Hans de Goede | 86b4909 | 2014-09-18 21:03:34 +0200 | [diff] [blame] | 403 | |
Hans de Goede | c13f60d | 2015-01-25 12:10:48 +0100 | [diff] [blame] | 404 | config GMAC_TX_DELAY |
| 405 | int "GMAC Transmit Clock Delay Chain" |
| 406 | default 0 |
| 407 | ---help--- |
| 408 | Set the GMAC Transmit Clock Delay Chain value. |
| 409 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 410 | endif |