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Jon Loeliger3dd2db52007-10-16 13:54:01 -05001/*
Kumar Gala6525d512010-07-08 22:37:44 -05002 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
Jon Loeliger3dd2db52007-10-16 13:54:01 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
Jon Loeligerc9974ab2008-01-04 11:58:23 -060022
Jon Loeliger3dd2db52007-10-16 13:54:01 -050023#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/immap_86xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050028#include <asm/fsl_pci.h>
Jon Loeliger39aa1a72008-08-26 15:01:36 -050029#include <asm/fsl_ddr_sdram.h>
Jon Loeligerc9974ab2008-01-04 11:58:23 -060030#include <i2c.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050031#include <asm/io.h>
Jon Loeliger1df170f2008-01-04 12:07:27 -060032#include <libfdt.h>
33#include <fdt_support.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060034#include <spd_sdram.h>
Ben Warren89973f82008-08-31 22:22:04 -070035#include <netdev.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050036
Jon Loeliger3dd2db52007-10-16 13:54:01 -050037void sdram_init(void);
Becky Bruce4c77de32008-10-31 17:13:32 -050038phys_size_t fixed_sdram(void);
Timur Tabie69e5202010-08-31 19:56:43 -050039int mpc8610hpcd_diu_init(void);
Jon Loeligerc9974ab2008-01-04 11:58:23 -060040
Jon Loeliger3dd2db52007-10-16 13:54:01 -050041
42/* called before any console output */
43int board_early_init_f(void)
44{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050046 volatile ccsr_gur_t *gur = &immap->im_gur;
47
York Suna8778802007-10-29 13:58:39 -050048 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
49
50 return 0;
51}
52
53int misc_init_r(void)
54{
55 u8 tmp_val, version;
Kumar Gala048e7ef2009-07-22 10:12:39 -050056 u8 *pixis_base = (u8 *)PIXIS_BASE;
York Suna8778802007-10-29 13:58:39 -050057
58 /*Do not use 8259PIC*/
Kumar Gala048e7ef2009-07-22 10:12:39 -050059 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
60 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
York Suna8778802007-10-29 13:58:39 -050061
62 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
Kumar Gala048e7ef2009-07-22 10:12:39 -050063 version = in_8(pixis_base + PIXIS_PVER);
York Suna8778802007-10-29 13:58:39 -050064 if(version >= 0x07) {
Kumar Gala048e7ef2009-07-22 10:12:39 -050065 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
66 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
York Suna8778802007-10-29 13:58:39 -050067 }
68
69 /* Using this for DIU init before the driver in linux takes over
70 * Enable the TFP410 Encoder (I2C address 0x38)
71 */
72
73 tmp_val = 0xBF;
74 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
75 /* Verify if enabled */
76 tmp_val = 0;
77 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
78 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
79
80 tmp_val = 0x10;
81 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
82 /* Verify if enabled */
83 tmp_val = 0;
84 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
85 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
86
Jon Loeliger3dd2db52007-10-16 13:54:01 -050087 return 0;
88}
89
90int checkboard(void)
91{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050093 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
Kumar Gala048e7ef2009-07-22 10:12:39 -050094 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050095
Wolfgang Denk9b55a252008-07-11 01:16:00 +020096 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
97 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
Kumar Gala048e7ef2009-07-22 10:12:39 -050098 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
99 in_8(pixis_base + PIXIS_PVER));
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500100
101 mcm->abcr |= 0x00010000; /* 0 */
102 mcm->hpmr3 = 0x80000008; /* 4c */
103 mcm->hpmr0 = 0;
104 mcm->hpmr1 = 0;
105 mcm->hpmr2 = 0;
106 mcm->hpmr4 = 0;
107 mcm->hpmr5 = 0;
108
109 return 0;
110}
111
112
Becky Bruce9973e3c2008-06-09 16:03:40 -0500113phys_size_t
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500114initdram(int board_type)
115{
Becky Bruce4c77de32008-10-31 17:13:32 -0500116 phys_size_t dram_size = 0;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500117
118#if defined(CONFIG_SPD_EEPROM)
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500119 dram_size = fsl_ddr_sdram();
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500120#else
121 dram_size = fixed_sdram();
122#endif
123
Timur Tabi9ff32d82010-03-29 12:51:07 -0500124 setup_ddr_bat(dram_size);
125
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500126 puts(" DDR: ");
127 return dram_size;
128}
129
130
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500131#if !defined(CONFIG_SPD_EEPROM)
132/*
133 * Fixed sdram init -- doesn't use serial presence detect.
134 */
135
Becky Bruce4c77de32008-10-31 17:13:32 -0500136phys_size_t fixed_sdram(void)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500137{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#if !defined(CONFIG_SYS_RAMBOOT)
139 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500140 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
141 uint d_init;
142
143 ddr->cs0_bnds = 0x0000001f;
144 ddr->cs0_config = 0x80010202;
145
Kumar Gala45239cf2008-04-29 10:27:08 -0500146 ddr->timing_cfg_3 = 0x00000000;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500147 ddr->timing_cfg_0 = 0x00260802;
148 ddr->timing_cfg_1 = 0x3935d322;
149 ddr->timing_cfg_2 = 0x14904cc8;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500150 ddr->sdram_mode = 0x00480432;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500151 ddr->sdram_mode_2 = 0x00000000;
152 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
153 ddr->sdram_data_init = 0xDEADBEEF;
154 ddr->sdram_clk_cntl = 0x03800000;
155 ddr->sdram_cfg_2 = 0x04400010;
156
157#if defined(CONFIG_DDR_ECC)
158 ddr->err_int_en = 0x0000000d;
159 ddr->err_disable = 0x00000000;
160 ddr->err_sbe = 0x00010000;
161#endif
162 asm("sync;isync");
163
164 udelay(500);
165
Peter Tysere7ee23e2009-07-17 10:14:45 -0500166 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500167
168
169#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
170 d_init = 1;
171 debug("DDR - 1st controller: memory initializing\n");
172 /*
173 * Poll until memory is initialized.
174 * 512 Meg at 400 might hit this 200 times or so.
175 */
176 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
177 udelay(1000);
178
179 debug("DDR: memory initialized\n\n");
180 asm("sync; isync");
181 udelay(500);
182#endif
183
184 return 512 * 1024 * 1024;
185#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500187}
188
189#endif
190
191#if defined(CONFIG_PCI)
192/*
193 * Initialize PCI Devices, report devices found.
194 */
195
196#ifndef CONFIG_PCI_PNP
197static struct pci_config_table pci_fsl86xxads_config_table[] = {
198 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
199 PCI_IDSEL_NUMBER, PCI_ANY_ID,
200 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
201 PCI_ENET0_MEMADDR,
202 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
203 {}
204};
205#endif
206
207
208static struct pci_controller pci1_hose = {
209#ifndef CONFIG_PCI_PNP
210config_table:pci_mpc86xxcts_config_table
211#endif
212};
213#endif /* CONFIG_PCI */
214
215#ifdef CONFIG_PCIE1
216static struct pci_controller pcie1_hose;
217#endif
218
219#ifdef CONFIG_PCIE2
220static struct pci_controller pcie2_hose;
221#endif
222
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500223void pci_init_board(void)
224{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500226 volatile ccsr_gur_t *gur = &immap->im_gur;
Kumar Gala5e3d7052009-11-04 12:51:10 -0600227 struct fsl_pci_info pci_info[3];
228 u32 devdisr, pordevsr, io_sel;
229 int first_free_busno = 0;
230 int num = 0;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500231
Kumar Gala5e3d7052009-11-04 12:51:10 -0600232 int pci_agent, pcie_ep, pcie_configured;
233
234 devdisr = in_be32(&gur->devdisr);
235 pordevsr = in_be32(&gur->pordevsr);
236 io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL)
237 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
238
239 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500240
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500241#ifdef CONFIG_PCIE1
Kumar Gala5e3d7052009-11-04 12:51:10 -0600242 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500243
Kumar Gala5e3d7052009-11-04 12:51:10 -0600244 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
245 SET_STD_PCIE_INFO(pci_info[num], 1);
246 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
247 printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
Peter Tyser64917ca2010-01-17 15:38:26 -0600248 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Gala5e3d7052009-11-04 12:51:10 -0600249 pci_info[num].regs);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500250
Kumar Gala5e3d7052009-11-04 12:51:10 -0600251 first_free_busno = fsl_pci_init_port(&pci_info[num++],
252 &pcie1_hose, first_free_busno);
253 } else {
254 printf (" PCIE1: disabled\n");
255 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500256
Kumar Gala5e3d7052009-11-04 12:51:10 -0600257 puts("\n");
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500258#else
Kumar Gala5e3d7052009-11-04 12:51:10 -0600259 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
260#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500261
262#ifdef CONFIG_PCIE2
Kumar Gala5e3d7052009-11-04 12:51:10 -0600263 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500264
Kumar Gala5e3d7052009-11-04 12:51:10 -0600265 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
266 SET_STD_PCIE_INFO(pci_info[num], 2);
267 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
268 printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
Peter Tyser64917ca2010-01-17 15:38:26 -0600269 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Gala5e3d7052009-11-04 12:51:10 -0600270 pci_info[num].regs);
271 first_free_busno = fsl_pci_init_port(&pci_info[num++],
272 &pcie2_hose, first_free_busno);
273 } else {
274 printf (" PCIE2: disabled\n");
275 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500276
Kumar Gala5e3d7052009-11-04 12:51:10 -0600277 puts("\n");
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500278#else
Kumar Gala5e3d7052009-11-04 12:51:10 -0600279 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
280#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500281
282#ifdef CONFIG_PCI1
Kumar Gala5e3d7052009-11-04 12:51:10 -0600283 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
284 SET_STD_PCI_INFO(pci_info[num], 1);
285 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500286 printf(" PCI connected to PCI slots as %s" \
Kumar Gala5e3d7052009-11-04 12:51:10 -0600287 " (base address %lx)\n",
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500288 pci_agent ? "Agent" : "Host",
Kumar Gala5e3d7052009-11-04 12:51:10 -0600289 pci_info[num].regs);
290 first_free_busno = fsl_pci_init_port(&pci_info[num++],
291 &pci1_hose, first_free_busno);
292 } else {
293 printf (" PCI: disabled\n");
294 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500295
Kumar Gala5e3d7052009-11-04 12:51:10 -0600296 puts("\n");
297#else
298 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
299#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500300}
301
Jon Loeliger1df170f2008-01-04 12:07:27 -0600302#if defined(CONFIG_OF_BOARD_SETUP)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500303void
304ft_board_setup(void *blob, bd_t *bd)
305{
Peter Tyser8439f052009-09-21 23:09:28 -0500306 ft_cpu_setup(blob, bd);
Jon Loeliger1df170f2008-01-04 12:07:27 -0600307
Kumar Gala6525d512010-07-08 22:37:44 -0500308 FT_FSL_PCI_SETUP;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500309}
310#endif
311
312/*
313 * get_board_sys_clk
314 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
315 */
316
317unsigned long
318get_board_sys_clk(ulong dummy)
319{
York Suna8778802007-10-29 13:58:39 -0500320 u8 i;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500321 ulong val = 0;
Kumar Gala048e7ef2009-07-22 10:12:39 -0500322 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500323
Kumar Gala048e7ef2009-07-22 10:12:39 -0500324 i = in_8(pixis_base + PIXIS_SPD);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500325 i &= 0x07;
326
327 switch (i) {
328 case 0:
329 val = 33333000;
330 break;
331 case 1:
332 val = 39999600;
333 break;
334 case 2:
335 val = 49999500;
336 break;
337 case 3:
338 val = 66666000;
339 break;
340 case 4:
341 val = 83332500;
342 break;
343 case 5:
344 val = 99999000;
345 break;
346 case 6:
347 val = 133332000;
348 break;
349 case 7:
350 val = 166665000;
351 break;
352 }
353
354 return val;
355}
Ben Warren65d3d992008-07-11 23:42:19 -0700356
Ben Warren65d3d992008-07-11 23:42:19 -0700357int board_eth_init(bd_t *bis)
358{
Ben Warren89973f82008-08-31 22:22:04 -0700359 return pci_eth_init(bis);
Ben Warren65d3d992008-07-11 23:42:19 -0700360}
Peter Tyser4ef630d2009-02-05 11:25:25 -0600361
362void board_reset(void)
363{
Kumar Gala048e7ef2009-07-22 10:12:39 -0500364 u8 *pixis_base = (u8 *)PIXIS_BASE;
365
366 out_8(pixis_base + PIXIS_RST, 0);
Peter Tyser4ef630d2009-02-05 11:25:25 -0600367
368 while (1)
369 ;
370}