blob: 02dc744065147029ac72283e63f036945e55591f [file] [log] [blame]
Jon Loeliger3dd2db52007-10-16 13:54:01 -05001/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
Jon Loeligerc9974ab2008-01-04 11:58:23 -060022
Jon Loeliger3dd2db52007-10-16 13:54:01 -050023#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/immap_86xx.h>
28#include <asm/immap_fsl_pci.h>
Jon Loeliger39aa1a72008-08-26 15:01:36 -050029#include <asm/fsl_ddr_sdram.h>
Jon Loeligerc9974ab2008-01-04 11:58:23 -060030#include <i2c.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050031#include <asm/io.h>
Jon Loeliger1df170f2008-01-04 12:07:27 -060032#include <libfdt.h>
33#include <fdt_support.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060034#include <spd_sdram.h>
Ben Warren89973f82008-08-31 22:22:04 -070035#include <netdev.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050036
37#include "../common/pixis.h"
38
Jon Loeliger3dd2db52007-10-16 13:54:01 -050039void sdram_init(void);
Becky Bruce4c77de32008-10-31 17:13:32 -050040phys_size_t fixed_sdram(void);
Jon Loeligerc9974ab2008-01-04 11:58:23 -060041void mpc8610hpcd_diu_init(void);
42
Jon Loeliger3dd2db52007-10-16 13:54:01 -050043
44/* called before any console output */
45int board_early_init_f(void)
46{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050048 volatile ccsr_gur_t *gur = &immap->im_gur;
49
York Suna8778802007-10-29 13:58:39 -050050 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
51
52 return 0;
53}
54
55int misc_init_r(void)
56{
57 u8 tmp_val, version;
58
59 /*Do not use 8259PIC*/
60 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
61 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
62
63 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
64 version = in8(PIXIS_BASE + PIXIS_PVER);
65 if(version >= 0x07) {
66 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
67 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
68 }
69
70 /* Using this for DIU init before the driver in linux takes over
71 * Enable the TFP410 Encoder (I2C address 0x38)
72 */
73
74 tmp_val = 0xBF;
75 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
76 /* Verify if enabled */
77 tmp_val = 0;
78 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
79 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
80
81 tmp_val = 0x10;
82 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
83 /* Verify if enabled */
84 tmp_val = 0;
85 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
86 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
87
88#ifdef CONFIG_FSL_DIU_FB
89 mpc8610hpcd_diu_init();
90#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -050091
92 return 0;
93}
94
95int checkboard(void)
96{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050098 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
99
Wolfgang Denk9b55a252008-07-11 01:16:00 +0200100 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
101 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
Kumar Galaa036b042008-06-19 01:45:50 -0500102 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
103 in8(PIXIS_BASE + PIXIS_PVER));
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500104
105 mcm->abcr |= 0x00010000; /* 0 */
106 mcm->hpmr3 = 0x80000008; /* 4c */
107 mcm->hpmr0 = 0;
108 mcm->hpmr1 = 0;
109 mcm->hpmr2 = 0;
110 mcm->hpmr4 = 0;
111 mcm->hpmr5 = 0;
112
113 return 0;
114}
115
116
Becky Bruce9973e3c2008-06-09 16:03:40 -0500117phys_size_t
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500118initdram(int board_type)
119{
Becky Bruce4c77de32008-10-31 17:13:32 -0500120 phys_size_t dram_size = 0;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500121
122#if defined(CONFIG_SPD_EEPROM)
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500123 dram_size = fsl_ddr_sdram();
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500124#else
125 dram_size = fixed_sdram();
126#endif
127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500129 puts(" DDR: ");
130 return dram_size;
131#endif
132
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500133 puts(" DDR: ");
134 return dram_size;
135}
136
137
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500138#if !defined(CONFIG_SPD_EEPROM)
139/*
140 * Fixed sdram init -- doesn't use serial presence detect.
141 */
142
Becky Bruce4c77de32008-10-31 17:13:32 -0500143phys_size_t fixed_sdram(void)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500144{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#if !defined(CONFIG_SYS_RAMBOOT)
146 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500147 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
148 uint d_init;
149
150 ddr->cs0_bnds = 0x0000001f;
151 ddr->cs0_config = 0x80010202;
152
Kumar Gala45239cf2008-04-29 10:27:08 -0500153 ddr->timing_cfg_3 = 0x00000000;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500154 ddr->timing_cfg_0 = 0x00260802;
155 ddr->timing_cfg_1 = 0x3935d322;
156 ddr->timing_cfg_2 = 0x14904cc8;
157 ddr->sdram_mode_1 = 0x00480432;
158 ddr->sdram_mode_2 = 0x00000000;
159 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
160 ddr->sdram_data_init = 0xDEADBEEF;
161 ddr->sdram_clk_cntl = 0x03800000;
162 ddr->sdram_cfg_2 = 0x04400010;
163
164#if defined(CONFIG_DDR_ECC)
165 ddr->err_int_en = 0x0000000d;
166 ddr->err_disable = 0x00000000;
167 ddr->err_sbe = 0x00010000;
168#endif
169 asm("sync;isync");
170
171 udelay(500);
172
173 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
174
175
176#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
177 d_init = 1;
178 debug("DDR - 1st controller: memory initializing\n");
179 /*
180 * Poll until memory is initialized.
181 * 512 Meg at 400 might hit this 200 times or so.
182 */
183 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
184 udelay(1000);
185
186 debug("DDR: memory initialized\n\n");
187 asm("sync; isync");
188 udelay(500);
189#endif
190
191 return 512 * 1024 * 1024;
192#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500194}
195
196#endif
197
198#if defined(CONFIG_PCI)
199/*
200 * Initialize PCI Devices, report devices found.
201 */
202
203#ifndef CONFIG_PCI_PNP
204static struct pci_config_table pci_fsl86xxads_config_table[] = {
205 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
206 PCI_IDSEL_NUMBER, PCI_ANY_ID,
207 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
208 PCI_ENET0_MEMADDR,
209 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
210 {}
211};
212#endif
213
214
215static struct pci_controller pci1_hose = {
216#ifndef CONFIG_PCI_PNP
217config_table:pci_mpc86xxcts_config_table
218#endif
219};
220#endif /* CONFIG_PCI */
221
222#ifdef CONFIG_PCIE1
223static struct pci_controller pcie1_hose;
224#endif
225
226#ifdef CONFIG_PCIE2
227static struct pci_controller pcie2_hose;
228#endif
229
230int first_free_busno = 0;
231
Kumar Galac2083e02008-10-22 14:38:55 -0500232extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
233extern void fsl_pci_init(struct pci_controller *hose);
234
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500235void pci_init_board(void)
236{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500238 volatile ccsr_gur_t *gur = &immap->im_gur;
239 uint devdisr = gur->devdisr;
Jon Loeligera551cee2008-02-20 14:22:26 -0600240 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
241 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
242 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
243 >> MPC8610_PORBMSR_HA_SHIFT;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500244
245 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
246 devdisr, io_sel, host_agent);
247
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500248#ifdef CONFIG_PCIE1
249 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500251 struct pci_controller *hose = &pcie1_hose;
252 int pcie_configured = (io_sel == 1) || (io_sel == 4);
253 int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
254 (host_agent == 5);
Kumar Galac2083e02008-10-22 14:38:55 -0500255 struct pci_region *r = hose->regions;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500256
257 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
258 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
259 pcie_ep ? "End Point" : "Root Complex",
260 (uint)pci);
261 if (pci->pme_msg_det)
262 pci->pme_msg_det = 0xffffffff;
263
264 /* inbound */
Kumar Galac2083e02008-10-22 14:38:55 -0500265 r += fsl_pci_setup_inbound_windows(r);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500266
267 /* outbound memory */
Kumar Galac2083e02008-10-22 14:38:55 -0500268 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269 CONFIG_SYS_PCIE1_MEM_BASE,
270 CONFIG_SYS_PCIE1_MEM_PHYS,
271 CONFIG_SYS_PCIE1_MEM_SIZE,
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500272 PCI_REGION_MEM);
273
274 /* outbound io */
Kumar Galac2083e02008-10-22 14:38:55 -0500275 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276 CONFIG_SYS_PCIE1_IO_BASE,
277 CONFIG_SYS_PCIE1_IO_PHYS,
278 CONFIG_SYS_PCIE1_IO_SIZE,
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500279 PCI_REGION_IO);
280
Kumar Galac2083e02008-10-22 14:38:55 -0500281 hose->region_count = r - hose->regions;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500282
283 hose->first_busno = first_free_busno;
284 pci_setup_indirect(hose, (int)&pci->cfg_addr,
285 (int)&pci->cfg_data);
286
287 fsl_pci_init(hose);
288
289 first_free_busno = hose->last_busno + 1;
290 printf(" PCI-Express 1 on bus %02x - %02x\n",
291 hose->first_busno, hose->last_busno);
292
293 } else
294 puts(" PCI-Express 1: Disabled\n");
295 }
296#else
297 puts("PCI-Express 1: Disabled\n");
298#endif /* CONFIG_PCIE1 */
299
300
301#ifdef CONFIG_PCIE2
302 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500304 struct pci_controller *hose = &pcie2_hose;
Kumar Galac2083e02008-10-22 14:38:55 -0500305 struct pci_region *r = hose->regions;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500306
307 int pcie_configured = (io_sel == 0) || (io_sel == 4);
308 int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
309 (host_agent == 4);
310
311 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
312 printf(" PCI-Express 2 connected to slot as %s" \
313 " (base address %x)\n",
314 pcie_ep ? "End Point" : "Root Complex",
315 (uint)pci);
316 if (pci->pme_msg_det)
317 pci->pme_msg_det = 0xffffffff;
318
319 /* inbound */
Kumar Galac2083e02008-10-22 14:38:55 -0500320 r += fsl_pci_setup_inbound_windows(r);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500321
322 /* outbound memory */
Kumar Galac2083e02008-10-22 14:38:55 -0500323 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324 CONFIG_SYS_PCIE2_MEM_BASE,
325 CONFIG_SYS_PCIE2_MEM_PHYS,
326 CONFIG_SYS_PCIE2_MEM_SIZE,
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500327 PCI_REGION_MEM);
328
329 /* outbound io */
Kumar Galac2083e02008-10-22 14:38:55 -0500330 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331 CONFIG_SYS_PCIE2_IO_BASE,
332 CONFIG_SYS_PCIE2_IO_PHYS,
333 CONFIG_SYS_PCIE2_IO_SIZE,
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500334 PCI_REGION_IO);
335
Kumar Galac2083e02008-10-22 14:38:55 -0500336 hose->region_count = r - hose->regions;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500337
338 hose->first_busno = first_free_busno;
339 pci_setup_indirect(hose, (int)&pci->cfg_addr,
340 (int)&pci->cfg_data);
341
342 fsl_pci_init(hose);
343
344 first_free_busno = hose->last_busno + 1;
345 printf(" PCI-Express 2 on bus %02x - %02x\n",
346 hose->first_busno, hose->last_busno);
347 } else
348 puts(" PCI-Express 2: Disabled\n");
349 }
350#else
351 puts("PCI-Express 2: Disabled\n");
352#endif /* CONFIG_PCIE2 */
353
354
355#ifdef CONFIG_PCI1
356 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500358 struct pci_controller *hose = &pci1_hose;
359 int pci_agent = (host_agent >= 4) && (host_agent <= 6);
Kumar Galac2083e02008-10-22 14:38:55 -0500360 struct pci_region *r = hose->regions;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500361
362 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
363 printf(" PCI connected to PCI slots as %s" \
364 " (base address %x)\n",
365 pci_agent ? "Agent" : "Host",
366 (uint)pci);
367
368 /* inbound */
Kumar Galac2083e02008-10-22 14:38:55 -0500369 r += fsl_pci_setup_inbound_windows(r);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500370
371 /* outbound memory */
Kumar Galac2083e02008-10-22 14:38:55 -0500372 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373 CONFIG_SYS_PCI1_MEM_BASE,
374 CONFIG_SYS_PCI1_MEM_PHYS,
375 CONFIG_SYS_PCI1_MEM_SIZE,
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500376 PCI_REGION_MEM);
377
378 /* outbound io */
Kumar Galac2083e02008-10-22 14:38:55 -0500379 pci_set_region(r++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380 CONFIG_SYS_PCI1_IO_BASE,
381 CONFIG_SYS_PCI1_IO_PHYS,
382 CONFIG_SYS_PCI1_IO_SIZE,
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500383 PCI_REGION_IO);
384
Kumar Galac2083e02008-10-22 14:38:55 -0500385 hose->region_count = r - hose->regions;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500386
387 hose->first_busno = first_free_busno;
388 pci_setup_indirect(hose, (int) &pci->cfg_addr,
389 (int) &pci->cfg_data);
390
391 fsl_pci_init(hose);
392
393 first_free_busno = hose->last_busno + 1;
394 printf(" PCI on bus %02x - %02x\n",
395 hose->first_busno, hose->last_busno);
396
397
398 } else
399 puts(" PCI: Disabled\n");
400 }
401#endif /* CONFIG_PCI1 */
402}
403
Jon Loeliger1df170f2008-01-04 12:07:27 -0600404#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Galac2083e02008-10-22 14:38:55 -0500405extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
406 struct pci_controller *hose);
407
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500408void
409ft_board_setup(void *blob, bd_t *bd)
410{
Jon Loeliger1df170f2008-01-04 12:07:27 -0600411 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
412 "timebase-frequency", bd->bi_busfreq / 4, 1);
413 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
414 "bus-frequency", bd->bi_busfreq, 1);
415 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
416 "clock-frequency", bd->bi_intfreq, 1);
417 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
418 "bus-frequency", bd->bi_busfreq, 1);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500419
Jon Loeliger1df170f2008-01-04 12:07:27 -0600420 do_fixup_by_compat_u32(blob, "ns16550",
421 "clock-frequency", bd->bi_busfreq, 1);
422
423 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
424
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500425#ifdef CONFIG_PCI1
Kumar Galac2083e02008-10-22 14:38:55 -0500426 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500427#endif
428#ifdef CONFIG_PCIE1
Kumar Galac2083e02008-10-22 14:38:55 -0500429 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500430#endif
431#ifdef CONFIG_PCIE2
Kumar Galac2083e02008-10-22 14:38:55 -0500432 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500433#endif
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500434}
435#endif
436
437/*
438 * get_board_sys_clk
439 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
440 */
441
442unsigned long
443get_board_sys_clk(ulong dummy)
444{
York Suna8778802007-10-29 13:58:39 -0500445 u8 i;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500446 ulong val = 0;
447 ulong a;
448
449 a = PIXIS_BASE + PIXIS_SPD;
450 i = in8(a);
451 i &= 0x07;
452
453 switch (i) {
454 case 0:
455 val = 33333000;
456 break;
457 case 1:
458 val = 39999600;
459 break;
460 case 2:
461 val = 49999500;
462 break;
463 case 3:
464 val = 66666000;
465 break;
466 case 4:
467 val = 83332500;
468 break;
469 case 5:
470 val = 99999000;
471 break;
472 case 6:
473 val = 133332000;
474 break;
475 case 7:
476 val = 166665000;
477 break;
478 }
479
480 return val;
481}
Ben Warren65d3d992008-07-11 23:42:19 -0700482
Ben Warren65d3d992008-07-11 23:42:19 -0700483int board_eth_init(bd_t *bis)
484{
Ben Warren89973f82008-08-31 22:22:04 -0700485 return pci_eth_init(bis);
Ben Warren65d3d992008-07-11 23:42:19 -0700486}