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Wolfgang Denkba94a1b2006-05-30 15:56:48 +02001/*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <malloc.h>
27#include <asm/arch/ixp425.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020031/* predefine these here for FPGA programming (before including fpga.c) */
32#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
34#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020035#define OLD_VAL old_val
36
37static unsigned long old_val = 0;
38
39/*
40 * include common fpga code (for prodrive boards)
41 */
42#include "../common/fpga.c"
43
44/*
45 * Miscelaneous platform dependent initialisations
46 */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020047int board_init(void)
48{
49 /* arch number of PDNB3 */
50 gd->bd->bi_arch_number = MACH_TYPE_PDNB3;
51
52 /* adress of boot parameters */
53 gd->bd->bi_boot_params = 0x00000100;
54
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
56 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020057
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
59 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020060
61 /*
62 * Setup GPIO's for FPGA programming
63 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
65 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
66 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
67 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
68 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
69 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
70 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
71 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020072
73 /*
74 * Setup GPIO's for interrupts
75 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
77 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
78 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
79 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
80 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
81 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
82 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
83 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020084
85 /*
86 * Setup GPIO's for 33MHz clock output
87 */
88 *IXP425_GPIO_GPCLKR = 0x01FF0000;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020090
91 /*
92 * Setup other chip select's
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094 *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020095
96 return 0;
97}
98
99/*
100 * Check Board Identity
101 */
102int checkboard(void)
103{
104 char *s = getenv("serial#");
105
106 puts("Board: PDNB3");
107
108 if (s != NULL) {
109 puts(", serial# ");
110 puts(s);
111 }
112 putc('\n');
113
114 return (0);
115}
116
117int dram_init(void)
118{
119 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
120 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
121
122 return (0);
123}
124
125int do_fpga_boot(unsigned char *fpgadata)
126{
127 unsigned char *dst;
128 int status;
129 int index;
130 int i;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 ulong len = CONFIG_SYS_MALLOC_LEN;
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200132
133 /*
134 * Setup GPIO's for FPGA programming
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
137 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
138 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200139
140 /*
141 * Save value so no readback is required upon programming
142 */
143 old_val = *IXP425_GPIO_GPOUTR;
144
145 /*
146 * First try to decompress fpga image (gzip compressed?)
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
149 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200150 printf("Error: Image has to be gzipp'ed!\n");
151 return -1;
152 }
153
154 status = fpga_boot(dst, len);
155 if (status != 0) {
156 printf("\nFPGA: Booting failed ");
157 switch (status) {
158 case ERROR_FPGA_PRG_INIT_LOW:
159 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
160 break;
161 case ERROR_FPGA_PRG_INIT_HIGH:
162 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
163 break;
164 case ERROR_FPGA_PRG_DONE:
165 printf("(Timeout: DONE not high after programming FPGA)\n ");
166 break;
167 }
168
169 /* display infos on fpgaimage */
170 index = 15;
171 for (i=0; i<4; i++) {
172 len = dst[index];
173 printf("FPGA: %s\n", &(dst[index+1]));
174 index += len+3;
175 }
176 putc ('\n');
177 /* delayed reboot */
178 for (i=5; i>0; i--) {
179 printf("Rebooting in %2d seconds \r",i);
180 for (index=0;index<1000;index++)
181 udelay(1000);
182 }
183 putc('\n');
184 do_reset(NULL, 0, 0, NULL);
185 }
186
187 puts("FPGA: ");
188
189 /* display infos on fpgaimage */
190 index = 15;
191 for (i=0; i<4; i++) {
192 len = dst[index];
193 printf("%s ", &(dst[index+1]));
194 index += len+3;
195 }
196 putc('\n');
197
198 free(dst);
199
200 /*
201 * Reset FPGA
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200204 udelay(10);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200206
207 return (0);
208}
209
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200210int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200211{
212 ulong addr;
213
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200214 if (argc < 2)
215 return cmd_usage(cmdtp);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200216
217 addr = simple_strtoul(argv[1], NULL, 16);
218
219 return do_fpga_boot((unsigned char *)addr);
220}
221
222U_BOOT_CMD(
223 fpga, 2, 0, do_fpga,
Peter Tyser2fb26042009-01-27 18:03:12 -0600224 "boot FPGA",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200225 "address size\n - boot FPGA with gzipped image at <address>"
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200226);
227
Jon Loeliger3fe00102007-07-09 18:38:39 -0500228#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200229extern struct pci_controller hose;
230extern void pci_ixp_init(struct pci_controller * hose);
231
232void pci_init_board(void)
233{
234 extern void pci_ixp_init (struct pci_controller *hose);
235
236 pci_ixp_init(&hose);
237}
238#endif