blob: afe5050e4d8084b4463dc0f74972224ea61c0629 [file] [log] [blame]
Joseph Chen2a950e32021-06-02 15:58:25 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_RK3568_COMMON_H
7#define __CONFIG_RK3568_COMMON_H
8
9#include "rockchip-common.h"
10
11#define CONFIG_SYS_CBSIZE 1024
Joseph Chen2a950e32021-06-02 15:58:25 +080012
13#define COUNTER_FREQUENCY 24000000
14#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020
15
16#define CONFIG_IRAM_BASE 0xfdcc0000
17
18#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
Joseph Chen2a950e32021-06-02 15:58:25 +080019#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
20
21#define CONFIG_SYS_SDRAM_BASE 0
22#define SDRAM_MAX_SIZE 0xf0000000
23
24#ifndef CONFIG_SPL_BUILD
25#define ENV_MEM_LAYOUT_SETTINGS \
26 "scriptaddr=0x00c00000\0" \
27 "pxefile_addr_r=0x00e00000\0" \
28 "fdt_addr_r=0x0a100000\0" \
29 "kernel_addr_r=0x02080000\0" \
30 "ramdisk_addr_r=0x0a200000\0"
31
32#include <config_distro_bootcmd.h>
33#define CONFIG_EXTRA_ENV_SETTINGS \
34 ENV_MEM_LAYOUT_SETTINGS \
35 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
36 "partitions=" PARTS_DEFAULT \
37 ROCKCHIP_DEVICE_SETTINGS \
38 BOOTENV
39#endif
40
41#endif