blob: b6568917ea8f214b9350095cde6c780e304ceddd [file] [log] [blame]
Joseph Chen2a950e32021-06-02 15:58:25 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_RK3568_COMMON_H
7#define __CONFIG_RK3568_COMMON_H
8
9#include "rockchip-common.h"
10
11#define CONFIG_SYS_CBSIZE 1024
12#define CONFIG_SKIP_LOWLEVEL_INIT
13
14#define COUNTER_FREQUENCY 24000000
15#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020
16
17#define CONFIG_IRAM_BASE 0xfdcc0000
18
19#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
20#define CONFIG_SYS_LOAD_ADDR 0x00c00800
21#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
22
23#define CONFIG_SYS_SDRAM_BASE 0
24#define SDRAM_MAX_SIZE 0xf0000000
25
26#ifndef CONFIG_SPL_BUILD
27#define ENV_MEM_LAYOUT_SETTINGS \
28 "scriptaddr=0x00c00000\0" \
29 "pxefile_addr_r=0x00e00000\0" \
30 "fdt_addr_r=0x0a100000\0" \
31 "kernel_addr_r=0x02080000\0" \
32 "ramdisk_addr_r=0x0a200000\0"
33
34#include <config_distro_bootcmd.h>
35#define CONFIG_EXTRA_ENV_SETTINGS \
36 ENV_MEM_LAYOUT_SETTINGS \
37 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
38 "partitions=" PARTS_DEFAULT \
39 ROCKCHIP_DEVICE_SETTINGS \
40 BOOTENV
41#endif
42
43#endif