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Jon Loeliger3dd2db52007-10-16 13:54:01 -05001/*
Zhao Chenhuid5c784e2011-08-24 13:20:06 +08002 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
Jon Loeliger3dd2db52007-10-16 13:54:01 -05003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Jon Loeliger3dd2db52007-10-16 13:54:01 -05005 */
Jon Loeligerc9974ab2008-01-04 11:58:23 -06006
Jon Loeliger3dd2db52007-10-16 13:54:01 -05007#include <common.h>
8#include <command.h>
9#include <pci.h>
10#include <asm/processor.h>
11#include <asm/immap_86xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050012#include <asm/fsl_pci.h>
York Sun5614e712013-09-30 09:22:09 -070013#include <fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060014#include <asm/fsl_serdes.h>
Jon Loeligerc9974ab2008-01-04 11:58:23 -060015#include <i2c.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050016#include <asm/io.h>
Jon Loeliger1df170f2008-01-04 12:07:27 -060017#include <libfdt.h>
18#include <fdt_support.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060019#include <spd_sdram.h>
Ben Warren89973f82008-08-31 22:22:04 -070020#include <netdev.h>
Jon Loeliger3dd2db52007-10-16 13:54:01 -050021
Jon Loeliger3dd2db52007-10-16 13:54:01 -050022void sdram_init(void);
Becky Bruce4c77de32008-10-31 17:13:32 -050023phys_size_t fixed_sdram(void);
Timur Tabie69e5202010-08-31 19:56:43 -050024int mpc8610hpcd_diu_init(void);
Jon Loeligerc9974ab2008-01-04 11:58:23 -060025
Jon Loeliger3dd2db52007-10-16 13:54:01 -050026
27/* called before any console output */
28int board_early_init_f(void)
29{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050031 volatile ccsr_gur_t *gur = &immap->im_gur;
32
York Suna8778802007-10-29 13:58:39 -050033 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
34
35 return 0;
36}
37
38int misc_init_r(void)
39{
40 u8 tmp_val, version;
Kumar Gala048e7ef2009-07-22 10:12:39 -050041 u8 *pixis_base = (u8 *)PIXIS_BASE;
York Suna8778802007-10-29 13:58:39 -050042
43 /*Do not use 8259PIC*/
Kumar Gala048e7ef2009-07-22 10:12:39 -050044 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
45 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
York Suna8778802007-10-29 13:58:39 -050046
47 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
Kumar Gala048e7ef2009-07-22 10:12:39 -050048 version = in_8(pixis_base + PIXIS_PVER);
York Suna8778802007-10-29 13:58:39 -050049 if(version >= 0x07) {
Kumar Gala048e7ef2009-07-22 10:12:39 -050050 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
51 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
York Suna8778802007-10-29 13:58:39 -050052 }
53
54 /* Using this for DIU init before the driver in linux takes over
55 * Enable the TFP410 Encoder (I2C address 0x38)
56 */
57
58 tmp_val = 0xBF;
59 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
60 /* Verify if enabled */
61 tmp_val = 0;
62 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
Marek Vasut7315ab22011-10-21 14:17:09 +000063 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
York Suna8778802007-10-29 13:58:39 -050064
65 tmp_val = 0x10;
66 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
67 /* Verify if enabled */
68 tmp_val = 0;
69 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
Marek Vasut7315ab22011-10-21 14:17:09 +000070 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
York Suna8778802007-10-29 13:58:39 -050071
Jon Loeliger3dd2db52007-10-16 13:54:01 -050072 return 0;
73}
74
75int checkboard(void)
76{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050078 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
Kumar Gala048e7ef2009-07-22 10:12:39 -050079 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger3dd2db52007-10-16 13:54:01 -050080
Timur Tabi26fd33b2011-04-28 13:41:20 -050081 printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
82 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
Kumar Gala048e7ef2009-07-22 10:12:39 -050083 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
84 in_8(pixis_base + PIXIS_PVER));
Jon Loeliger3dd2db52007-10-16 13:54:01 -050085
Timur Tabi26fd33b2011-04-28 13:41:20 -050086 /*
87 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
88 * bank and LBMAP=00 is the alternate bank. However, the pixis
89 * altbank code can only set bits, not clear them, so we treat 00 as
90 * the normal bank and 11 as the alternate.
91 */
92 switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
93 case 0:
94 puts("vBank: Standard\n");
95 break;
96 case 0x40:
97 puts("Promjet\n");
98 break;
99 case 0x80:
100 puts("NAND\n");
101 break;
102 case 0xC0:
103 puts("vBank: Alternate\n");
104 break;
105 }
106
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500107 mcm->abcr |= 0x00010000; /* 0 */
108 mcm->hpmr3 = 0x80000008; /* 4c */
109 mcm->hpmr0 = 0;
110 mcm->hpmr1 = 0;
111 mcm->hpmr2 = 0;
112 mcm->hpmr4 = 0;
113 mcm->hpmr5 = 0;
114
115 return 0;
116}
117
118
Becky Bruce9973e3c2008-06-09 16:03:40 -0500119phys_size_t
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500120initdram(int board_type)
121{
Becky Bruce4c77de32008-10-31 17:13:32 -0500122 phys_size_t dram_size = 0;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500123
124#if defined(CONFIG_SPD_EEPROM)
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500125 dram_size = fsl_ddr_sdram();
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500126#else
127 dram_size = fixed_sdram();
128#endif
129
Timur Tabi9ff32d82010-03-29 12:51:07 -0500130 setup_ddr_bat(dram_size);
131
Wolfgang Denk21cd5812011-07-25 10:13:53 +0200132 debug(" DDR: ");
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500133 return dram_size;
134}
135
136
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500137#if !defined(CONFIG_SPD_EEPROM)
138/*
139 * Fixed sdram init -- doesn't use serial presence detect.
140 */
141
Becky Bruce4c77de32008-10-31 17:13:32 -0500142phys_size_t fixed_sdram(void)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500143{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#if !defined(CONFIG_SYS_RAMBOOT)
145 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
York Sun9a17eb52013-11-18 10:29:32 -0800146 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500147 uint d_init;
148
149 ddr->cs0_bnds = 0x0000001f;
150 ddr->cs0_config = 0x80010202;
151
Kumar Gala45239cf2008-04-29 10:27:08 -0500152 ddr->timing_cfg_3 = 0x00000000;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500153 ddr->timing_cfg_0 = 0x00260802;
154 ddr->timing_cfg_1 = 0x3935d322;
155 ddr->timing_cfg_2 = 0x14904cc8;
Peter Tysere7ee23e2009-07-17 10:14:45 -0500156 ddr->sdram_mode = 0x00480432;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500157 ddr->sdram_mode_2 = 0x00000000;
158 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
159 ddr->sdram_data_init = 0xDEADBEEF;
160 ddr->sdram_clk_cntl = 0x03800000;
161 ddr->sdram_cfg_2 = 0x04400010;
162
163#if defined(CONFIG_DDR_ECC)
164 ddr->err_int_en = 0x0000000d;
165 ddr->err_disable = 0x00000000;
166 ddr->err_sbe = 0x00010000;
167#endif
168 asm("sync;isync");
169
170 udelay(500);
171
Peter Tysere7ee23e2009-07-17 10:14:45 -0500172 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500173
174
175#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
176 d_init = 1;
177 debug("DDR - 1st controller: memory initializing\n");
178 /*
179 * Poll until memory is initialized.
180 * 512 Meg at 400 might hit this 200 times or so.
181 */
182 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
183 udelay(1000);
184
185 debug("DDR: memory initialized\n\n");
186 asm("sync; isync");
187 udelay(500);
188#endif
189
190 return 512 * 1024 * 1024;
191#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500193}
194
195#endif
196
197#if defined(CONFIG_PCI)
198/*
199 * Initialize PCI Devices, report devices found.
200 */
201
202#ifndef CONFIG_PCI_PNP
203static struct pci_config_table pci_fsl86xxads_config_table[] = {
204 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
205 PCI_IDSEL_NUMBER, PCI_ANY_ID,
206 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
207 PCI_ENET0_MEMADDR,
208 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
209 {}
210};
211#endif
212
213
Zhao Chenhuid5c784e2011-08-24 13:20:06 +0800214static struct pci_controller pci1_hose;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500215#endif /* CONFIG_PCI */
216
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500217void pci_init_board(void)
218{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500220 volatile ccsr_gur_t *gur = &immap->im_gur;
Kumar Galab8526212010-12-17 10:42:33 -0600221 struct fsl_pci_info pci_info;
Wolfgang Denke38cc2c2011-11-29 22:17:54 +0000222 u32 devdisr;
Kumar Galab8526212010-12-17 10:42:33 -0600223 int first_free_busno;
224 int pci_agent;
Kumar Gala5e3d7052009-11-04 12:51:10 -0600225
226 devdisr = in_be32(&gur->devdisr);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500227
Kumar Galab8526212010-12-17 10:42:33 -0600228 first_free_busno = fsl_pcie_init_board(0);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500229
230#ifdef CONFIG_PCI1
Kumar Gala5e3d7052009-11-04 12:51:10 -0600231 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
Kumar Galab8526212010-12-17 10:42:33 -0600232 SET_STD_PCI_INFO(pci_info, 1);
233 set_next_law(pci_info.mem_phys,
234 law_size_bits(pci_info.mem_size), pci_info.law);
235 set_next_law(pci_info.io_phys,
236 law_size_bits(pci_info.io_size), pci_info.law);
237
238 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500239 printf("PCI: connected to PCI slots as %s" \
Kumar Gala5e3d7052009-11-04 12:51:10 -0600240 " (base address %lx)\n",
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500241 pci_agent ? "Agent" : "Host",
Kumar Galab8526212010-12-17 10:42:33 -0600242 pci_info.regs);
Zhao Chenhuid5c784e2011-08-24 13:20:06 +0800243#ifndef CONFIG_PCI_PNP
244 pci1_hose.config_table = pci_mpc86xxcts_config_table;
245#endif
Kumar Galab8526212010-12-17 10:42:33 -0600246 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala5e3d7052009-11-04 12:51:10 -0600247 &pci1_hose, first_free_busno);
248 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500249 printf("PCI: disabled\n");
Kumar Gala5e3d7052009-11-04 12:51:10 -0600250 }
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500251
Kumar Gala5e3d7052009-11-04 12:51:10 -0600252 puts("\n");
253#else
254 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
255#endif
Kumar Galab8526212010-12-17 10:42:33 -0600256
257 fsl_pcie_init_board(first_free_busno);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500258}
259
Jon Loeliger1df170f2008-01-04 12:07:27 -0600260#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600261int ft_board_setup(void *blob, bd_t *bd)
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500262{
Peter Tyser8439f052009-09-21 23:09:28 -0500263 ft_cpu_setup(blob, bd);
Jon Loeliger1df170f2008-01-04 12:07:27 -0600264
Kumar Gala6525d512010-07-08 22:37:44 -0500265 FT_FSL_PCI_SETUP;
Simon Glasse895a4b2014-10-23 18:58:47 -0600266
267 return 0;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500268}
269#endif
270
271/*
272 * get_board_sys_clk
273 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
274 */
275
276unsigned long
277get_board_sys_clk(ulong dummy)
278{
York Suna8778802007-10-29 13:58:39 -0500279 u8 i;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500280 ulong val = 0;
Kumar Gala048e7ef2009-07-22 10:12:39 -0500281 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500282
Kumar Gala048e7ef2009-07-22 10:12:39 -0500283 i = in_8(pixis_base + PIXIS_SPD);
Jon Loeliger3dd2db52007-10-16 13:54:01 -0500284 i &= 0x07;
285
286 switch (i) {
287 case 0:
288 val = 33333000;
289 break;
290 case 1:
291 val = 39999600;
292 break;
293 case 2:
294 val = 49999500;
295 break;
296 case 3:
297 val = 66666000;
298 break;
299 case 4:
300 val = 83332500;
301 break;
302 case 5:
303 val = 99999000;
304 break;
305 case 6:
306 val = 133332000;
307 break;
308 case 7:
309 val = 166665000;
310 break;
311 }
312
313 return val;
314}
Ben Warren65d3d992008-07-11 23:42:19 -0700315
Ben Warren65d3d992008-07-11 23:42:19 -0700316int board_eth_init(bd_t *bis)
317{
Ben Warren89973f82008-08-31 22:22:04 -0700318 return pci_eth_init(bis);
Ben Warren65d3d992008-07-11 23:42:19 -0700319}
Peter Tyser4ef630d2009-02-05 11:25:25 -0600320
321void board_reset(void)
322{
Kumar Gala048e7ef2009-07-22 10:12:39 -0500323 u8 *pixis_base = (u8 *)PIXIS_BASE;
324
325 out_8(pixis_base + PIXIS_RST, 0);
Peter Tyser4ef630d2009-02-05 11:25:25 -0600326
327 while (1)
328 ;
329}