blob: 2cf55cb743d71ba2532d3a41029011349167b14d [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassff3e0772015-03-05 12:25:25 -07002/*
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Simon Glassff3e0772015-03-05 12:25:25 -07005 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
Simon Glassff3e0772015-03-05 12:25:25 -070010#include <pci.h>
Simon Glass21d1fe72015-11-29 13:18:03 -070011#include <asm/io.h>
Simon Glassff3e0772015-03-05 12:25:25 -070012#include <dm/device-internal.h>
Simon Glassbf501592017-05-18 20:09:51 -060013#include <dm/lists.h>
Bin Meng348b7442015-08-20 06:40:23 -070014#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
15#include <asm/fsp/fsp_support.h>
16#endif
Simon Glass5e23b8b2015-11-29 13:17:49 -070017#include "pci_internal.h"
Simon Glassff3e0772015-03-05 12:25:25 -070018
19DECLARE_GLOBAL_DATA_PTR;
20
Simon Glassa6eb93b2016-01-18 20:19:14 -070021int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass983c6ba22015-08-31 18:55:35 -060022{
23 int ret;
24
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
26
27 /* Since buses may not be numbered yet try a little harder with bus 0 */
28 if (ret == -ENODEV) {
Simon Glass3f603cb2016-02-11 13:23:26 -070029 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass983c6ba22015-08-31 18:55:35 -060030 if (ret)
31 return ret;
Simon Glass983c6ba22015-08-31 18:55:35 -060032 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
33 }
34
35 return ret;
36}
37
Simon Glass9f60fb02015-11-19 20:27:00 -070038struct udevice *pci_get_controller(struct udevice *dev)
39{
40 while (device_is_on_pci_bus(dev))
41 dev = dev->parent;
42
43 return dev;
44}
45
Simon Glass21ccce12015-11-29 13:17:47 -070046pci_dev_t dm_pci_get_bdf(struct udevice *dev)
Simon Glass4b515e42015-07-06 16:47:46 -060047{
48 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
49 struct udevice *bus = dev->parent;
50
51 return PCI_ADD_BUS(bus->seq, pplat->devfn);
52}
53
Simon Glassff3e0772015-03-05 12:25:25 -070054/**
55 * pci_get_bus_max() - returns the bus number of the last active bus
56 *
57 * @return last bus number, or -1 if no active buses
58 */
59static int pci_get_bus_max(void)
60{
61 struct udevice *bus;
62 struct uclass *uc;
63 int ret = -1;
64
65 ret = uclass_get(UCLASS_PCI, &uc);
66 uclass_foreach_dev(bus, uc) {
67 if (bus->seq > ret)
68 ret = bus->seq;
69 }
70
71 debug("%s: ret=%d\n", __func__, ret);
72
73 return ret;
74}
75
76int pci_last_busno(void)
77{
Bin Meng069155c2015-10-01 00:36:01 -070078 return pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -070079}
80
81int pci_get_ff(enum pci_size_t size)
82{
83 switch (size) {
84 case PCI_SIZE_8:
85 return 0xff;
86 case PCI_SIZE_16:
87 return 0xffff;
88 default:
89 return 0xffffffff;
90 }
91}
92
Marek Vasut02e4d382018-10-10 21:27:06 +020093static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
94 ofnode *rnode)
95{
96 struct fdt_pci_addr addr;
97 ofnode node;
98 int ret;
99
100 dev_for_each_subnode(node, bus) {
101 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
102 &addr);
103 if (ret)
104 continue;
105
106 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
107 continue;
108
109 *rnode = node;
110 break;
111 }
112};
113
Simon Glassff3e0772015-03-05 12:25:25 -0700114int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
115 struct udevice **devp)
116{
117 struct udevice *dev;
118
119 for (device_find_first_child(bus, &dev);
120 dev;
121 device_find_next_child(&dev)) {
122 struct pci_child_platdata *pplat;
123
124 pplat = dev_get_parent_platdata(dev);
125 if (pplat && pplat->devfn == find_devfn) {
126 *devp = dev;
127 return 0;
128 }
129 }
130
131 return -ENODEV;
132}
133
Simon Glassf3f1fae2015-11-29 13:17:48 -0700134int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassff3e0772015-03-05 12:25:25 -0700135{
136 struct udevice *bus;
137 int ret;
138
Simon Glass983c6ba22015-08-31 18:55:35 -0600139 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700140 if (ret)
141 return ret;
142 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
143}
144
145static int pci_device_matches_ids(struct udevice *dev,
146 struct pci_device_id *ids)
147{
148 struct pci_child_platdata *pplat;
149 int i;
150
151 pplat = dev_get_parent_platdata(dev);
152 if (!pplat)
153 return -EINVAL;
154 for (i = 0; ids[i].vendor != 0; i++) {
155 if (pplat->vendor == ids[i].vendor &&
156 pplat->device == ids[i].device)
157 return i;
158 }
159
160 return -EINVAL;
161}
162
163int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
164 int *indexp, struct udevice **devp)
165{
166 struct udevice *dev;
167
168 /* Scan all devices on this bus */
169 for (device_find_first_child(bus, &dev);
170 dev;
171 device_find_next_child(&dev)) {
172 if (pci_device_matches_ids(dev, ids) >= 0) {
173 if ((*indexp)-- <= 0) {
174 *devp = dev;
175 return 0;
176 }
177 }
178 }
179
180 return -ENODEV;
181}
182
183int pci_find_device_id(struct pci_device_id *ids, int index,
184 struct udevice **devp)
185{
186 struct udevice *bus;
187
188 /* Scan all known buses */
189 for (uclass_first_device(UCLASS_PCI, &bus);
190 bus;
191 uclass_next_device(&bus)) {
192 if (!pci_bus_find_devices(bus, ids, &index, devp))
193 return 0;
194 }
195 *devp = NULL;
196
197 return -ENODEV;
198}
199
Simon Glass5c0bf642015-11-29 13:17:50 -0700200static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
201 unsigned int device, int *indexp,
202 struct udevice **devp)
203{
204 struct pci_child_platdata *pplat;
205 struct udevice *dev;
206
207 for (device_find_first_child(bus, &dev);
208 dev;
209 device_find_next_child(&dev)) {
210 pplat = dev_get_parent_platdata(dev);
211 if (pplat->vendor == vendor && pplat->device == device) {
212 if (!(*indexp)--) {
213 *devp = dev;
214 return 0;
215 }
216 }
217 }
218
219 return -ENODEV;
220}
221
222int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
223 struct udevice **devp)
224{
225 struct udevice *bus;
226
227 /* Scan all known buses */
228 for (uclass_first_device(UCLASS_PCI, &bus);
229 bus;
230 uclass_next_device(&bus)) {
231 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
232 return device_probe(*devp);
233 }
234 *devp = NULL;
235
236 return -ENODEV;
237}
238
Simon Glassa0eb8352015-11-29 13:17:52 -0700239int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
240{
241 struct udevice *dev;
242
243 /* Scan all known buses */
244 for (pci_find_first_device(&dev);
245 dev;
246 pci_find_next_device(&dev)) {
247 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
248
249 if (pplat->class == find_class && !index--) {
250 *devp = dev;
251 return device_probe(*devp);
252 }
253 }
254 *devp = NULL;
255
256 return -ENODEV;
257}
258
Simon Glassff3e0772015-03-05 12:25:25 -0700259int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
260 unsigned long value, enum pci_size_t size)
261{
262 struct dm_pci_ops *ops;
263
264 ops = pci_get_ops(bus);
265 if (!ops->write_config)
266 return -ENOSYS;
267 return ops->write_config(bus, bdf, offset, value, size);
268}
269
Simon Glass319dba12016-03-06 19:27:52 -0700270int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
271 u32 clr, u32 set)
272{
273 ulong val;
274 int ret;
275
276 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
277 if (ret)
278 return ret;
279 val &= ~clr;
280 val |= set;
281
282 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
283}
284
Simon Glassff3e0772015-03-05 12:25:25 -0700285int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
286 enum pci_size_t size)
287{
288 struct udevice *bus;
289 int ret;
290
Simon Glass983c6ba22015-08-31 18:55:35 -0600291 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700292 if (ret)
293 return ret;
294
Bin Meng4d8615c2015-07-19 00:20:04 +0800295 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700296}
297
Simon Glass66afb4e2015-08-10 07:05:03 -0600298int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
299 enum pci_size_t size)
300{
301 struct udevice *bus;
302
Bin Meng1e0f2262015-09-11 03:24:34 -0700303 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600304 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700305 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
306 size);
Simon Glass66afb4e2015-08-10 07:05:03 -0600307}
308
Simon Glassff3e0772015-03-05 12:25:25 -0700309int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
310{
311 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
312}
313
314int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
315{
316 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
317}
318
319int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
320{
321 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
322}
323
Simon Glass66afb4e2015-08-10 07:05:03 -0600324int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
325{
326 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
327}
328
329int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
330{
331 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
332}
333
334int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
335{
336 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
337}
338
Simon Glassff3e0772015-03-05 12:25:25 -0700339int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
340 unsigned long *valuep, enum pci_size_t size)
341{
342 struct dm_pci_ops *ops;
343
344 ops = pci_get_ops(bus);
345 if (!ops->read_config)
346 return -ENOSYS;
347 return ops->read_config(bus, bdf, offset, valuep, size);
348}
349
350int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
351 enum pci_size_t size)
352{
353 struct udevice *bus;
354 int ret;
355
Simon Glass983c6ba22015-08-31 18:55:35 -0600356 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700357 if (ret)
358 return ret;
359
Bin Meng4d8615c2015-07-19 00:20:04 +0800360 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700361}
362
Simon Glass66afb4e2015-08-10 07:05:03 -0600363int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
364 enum pci_size_t size)
365{
366 struct udevice *bus;
367
Bin Meng1e0f2262015-09-11 03:24:34 -0700368 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600369 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700370 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass66afb4e2015-08-10 07:05:03 -0600371 size);
372}
373
Simon Glassff3e0772015-03-05 12:25:25 -0700374int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
375{
376 unsigned long value;
377 int ret;
378
379 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
380 if (ret)
381 return ret;
382 *valuep = value;
383
384 return 0;
385}
386
387int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
388{
389 unsigned long value;
390 int ret;
391
392 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
393 if (ret)
394 return ret;
395 *valuep = value;
396
397 return 0;
398}
399
400int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
401{
402 unsigned long value;
403 int ret;
404
405 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
406 if (ret)
407 return ret;
408 *valuep = value;
409
410 return 0;
411}
412
Simon Glass66afb4e2015-08-10 07:05:03 -0600413int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
414{
415 unsigned long value;
416 int ret;
417
418 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
419 if (ret)
420 return ret;
421 *valuep = value;
422
423 return 0;
424}
425
426int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
427{
428 unsigned long value;
429 int ret;
430
431 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
432 if (ret)
433 return ret;
434 *valuep = value;
435
436 return 0;
437}
438
439int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
440{
441 unsigned long value;
442 int ret;
443
444 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
445 if (ret)
446 return ret;
447 *valuep = value;
448
449 return 0;
450}
451
Simon Glass319dba12016-03-06 19:27:52 -0700452int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
453{
454 u8 val;
455 int ret;
456
457 ret = dm_pci_read_config8(dev, offset, &val);
458 if (ret)
459 return ret;
460 val &= ~clr;
461 val |= set;
462
463 return dm_pci_write_config8(dev, offset, val);
464}
465
466int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
467{
468 u16 val;
469 int ret;
470
471 ret = dm_pci_read_config16(dev, offset, &val);
472 if (ret)
473 return ret;
474 val &= ~clr;
475 val |= set;
476
477 return dm_pci_write_config16(dev, offset, val);
478}
479
480int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
481{
482 u32 val;
483 int ret;
484
485 ret = dm_pci_read_config32(dev, offset, &val);
486 if (ret)
487 return ret;
488 val &= ~clr;
489 val |= set;
490
491 return dm_pci_write_config32(dev, offset, val);
492}
493
Bin Mengbbbcb522015-10-01 00:36:02 -0700494static void set_vga_bridge_bits(struct udevice *dev)
495{
496 struct udevice *parent = dev->parent;
497 u16 bc;
498
499 while (parent->seq != 0) {
500 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
501 bc |= PCI_BRIDGE_CTL_VGA;
502 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
503 parent = parent->parent;
504 }
505}
506
Simon Glassff3e0772015-03-05 12:25:25 -0700507int pci_auto_config_devices(struct udevice *bus)
508{
509 struct pci_controller *hose = bus->uclass_priv;
Bin Mengbbbcb522015-10-01 00:36:02 -0700510 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -0700511 unsigned int sub_bus;
512 struct udevice *dev;
513 int ret;
514
515 sub_bus = bus->seq;
516 debug("%s: start\n", __func__);
517 pciauto_config_init(hose);
518 for (ret = device_find_first_child(bus, &dev);
519 !ret && dev;
520 ret = device_find_next_child(&dev)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700521 unsigned int max_bus;
Simon Glass4d214552015-09-08 17:52:47 -0600522 int ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700523
Simon Glassff3e0772015-03-05 12:25:25 -0700524 debug("%s: device %s\n", __func__, dev->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700525 ret = dm_pciauto_config_device(dev);
Simon Glass4d214552015-09-08 17:52:47 -0600526 if (ret < 0)
527 return ret;
528 max_bus = ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700529 sub_bus = max(sub_bus, max_bus);
Bin Mengbbbcb522015-10-01 00:36:02 -0700530
531 pplat = dev_get_parent_platdata(dev);
532 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
533 set_vga_bridge_bits(dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700534 }
535 debug("%s: done\n", __func__);
536
537 return sub_bus;
538}
539
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +0300540int pci_generic_mmap_write_config(
541 struct udevice *bus,
542 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
543 pci_dev_t bdf,
544 uint offset,
545 ulong value,
546 enum pci_size_t size)
547{
548 void *address;
549
550 if (addr_f(bus, bdf, offset, &address) < 0)
551 return 0;
552
553 switch (size) {
554 case PCI_SIZE_8:
555 writeb(value, address);
556 return 0;
557 case PCI_SIZE_16:
558 writew(value, address);
559 return 0;
560 case PCI_SIZE_32:
561 writel(value, address);
562 return 0;
563 default:
564 return -EINVAL;
565 }
566}
567
568int pci_generic_mmap_read_config(
569 struct udevice *bus,
570 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
571 pci_dev_t bdf,
572 uint offset,
573 ulong *valuep,
574 enum pci_size_t size)
575{
576 void *address;
577
578 if (addr_f(bus, bdf, offset, &address) < 0) {
579 *valuep = pci_get_ff(size);
580 return 0;
581 }
582
583 switch (size) {
584 case PCI_SIZE_8:
585 *valuep = readb(address);
586 return 0;
587 case PCI_SIZE_16:
588 *valuep = readw(address);
589 return 0;
590 case PCI_SIZE_32:
591 *valuep = readl(address);
592 return 0;
593 default:
594 return -EINVAL;
595 }
596}
597
Simon Glass5e23b8b2015-11-29 13:17:49 -0700598int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassff3e0772015-03-05 12:25:25 -0700599{
Simon Glassff3e0772015-03-05 12:25:25 -0700600 int sub_bus;
601 int ret;
602
603 debug("%s\n", __func__);
Simon Glassff3e0772015-03-05 12:25:25 -0700604
605 sub_bus = pci_get_bus_max() + 1;
606 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700607 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700608
609 ret = device_probe(bus);
610 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600611 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassff3e0772015-03-05 12:25:25 -0700612 ret);
613 return ret;
614 }
615 if (sub_bus != bus->seq) {
616 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
617 __func__, bus->name, bus->seq, sub_bus);
618 return -EPIPE;
619 }
620 sub_bus = pci_get_bus_max();
Simon Glass5e23b8b2015-11-29 13:17:49 -0700621 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700622
623 return sub_bus;
624}
625
Simon Glassaba92962015-07-06 16:47:44 -0600626/**
627 * pci_match_one_device - Tell if a PCI device structure has a matching
628 * PCI device id structure
629 * @id: single PCI device id structure to match
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800630 * @find: the PCI device id structure to match against
Simon Glassaba92962015-07-06 16:47:44 -0600631 *
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800632 * Returns true if the finding pci_device_id structure matched or false if
633 * there is no match.
Simon Glassaba92962015-07-06 16:47:44 -0600634 */
635static bool pci_match_one_id(const struct pci_device_id *id,
636 const struct pci_device_id *find)
637{
638 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
639 (id->device == PCI_ANY_ID || id->device == find->device) &&
640 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
641 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
642 !((id->class ^ find->class) & id->class_mask))
643 return true;
644
645 return false;
646}
647
648/**
649 * pci_find_and_bind_driver() - Find and bind the right PCI driver
650 *
651 * This only looks at certain fields in the descriptor.
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600652 *
653 * @parent: Parent bus
654 * @find_id: Specification of the driver to find
655 * @bdf: Bus/device/function addreess - see PCI_BDF()
656 * @devp: Returns a pointer to the device created
657 * @return 0 if OK, -EPERM if the device is not needed before relocation and
658 * therefore was not created, other -ve value on error
Simon Glassaba92962015-07-06 16:47:44 -0600659 */
660static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600661 struct pci_device_id *find_id,
662 pci_dev_t bdf, struct udevice **devp)
Simon Glassaba92962015-07-06 16:47:44 -0600663{
664 struct pci_driver_entry *start, *entry;
Marek Vasut02e4d382018-10-10 21:27:06 +0200665 ofnode node = ofnode_null();
Simon Glassaba92962015-07-06 16:47:44 -0600666 const char *drv;
667 int n_ents;
668 int ret;
669 char name[30], *str;
Bin Meng08fc7b82015-08-20 06:40:17 -0700670 bool bridge;
Simon Glassaba92962015-07-06 16:47:44 -0600671
672 *devp = NULL;
673
674 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
675 find_id->vendor, find_id->device);
Marek Vasut02e4d382018-10-10 21:27:06 +0200676
677 /* Determine optional OF node */
678 pci_dev_find_ofnode(parent, bdf, &node);
679
Simon Glassaba92962015-07-06 16:47:44 -0600680 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
681 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
682 for (entry = start; entry != start + n_ents; entry++) {
683 const struct pci_device_id *id;
684 struct udevice *dev;
685 const struct driver *drv;
686
687 for (id = entry->match;
688 id->vendor || id->subvendor || id->class_mask;
689 id++) {
690 if (!pci_match_one_id(id, find_id))
691 continue;
692
693 drv = entry->driver;
Bin Meng08fc7b82015-08-20 06:40:17 -0700694
695 /*
696 * In the pre-relocation phase, we only bind devices
697 * whose driver has the DM_FLAG_PRE_RELOC set, to save
698 * precious memory space as on some platforms as that
699 * space is pretty limited (ie: using Cache As RAM).
700 */
701 if (!(gd->flags & GD_FLG_RELOC) &&
702 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600703 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700704
Simon Glassaba92962015-07-06 16:47:44 -0600705 /*
706 * We could pass the descriptor to the driver as
707 * platdata (instead of NULL) and allow its bind()
708 * method to return -ENOENT if it doesn't support this
709 * device. That way we could continue the search to
710 * find another driver. For now this doesn't seem
711 * necesssary, so just bind the first match.
712 */
Marek Vasut02e4d382018-10-10 21:27:06 +0200713 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
714 node, &dev);
Simon Glassaba92962015-07-06 16:47:44 -0600715 if (ret)
716 goto error;
717 debug("%s: Match found: %s\n", __func__, drv->name);
Bin Menged698aa2018-08-03 01:14:44 -0700718 dev->driver_data = id->driver_data;
Simon Glassaba92962015-07-06 16:47:44 -0600719 *devp = dev;
720 return 0;
721 }
722 }
723
Bin Meng08fc7b82015-08-20 06:40:17 -0700724 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
725 /*
726 * In the pre-relocation phase, we only bind bridge devices to save
727 * precious memory space as on some platforms as that space is pretty
728 * limited (ie: using Cache As RAM).
729 */
730 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600731 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700732
Simon Glassaba92962015-07-06 16:47:44 -0600733 /* Bind a generic driver so that the device can be used */
Bin Meng4d8615c2015-07-19 00:20:04 +0800734 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
735 PCI_FUNC(bdf));
Simon Glassaba92962015-07-06 16:47:44 -0600736 str = strdup(name);
737 if (!str)
738 return -ENOMEM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700739 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
740
Marek Vasut02e4d382018-10-10 21:27:06 +0200741 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
Simon Glassaba92962015-07-06 16:47:44 -0600742 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600743 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
xypron.glpk@gmx.dec42640c2017-05-08 20:40:16 +0200744 free(str);
Simon Glassaba92962015-07-06 16:47:44 -0600745 return ret;
746 }
747 debug("%s: No match found: bound generic driver instead\n", __func__);
748
749 return 0;
750
751error:
752 debug("%s: No match found: error %d\n", __func__, ret);
753 return ret;
754}
755
Simon Glassff3e0772015-03-05 12:25:25 -0700756int pci_bind_bus_devices(struct udevice *bus)
757{
758 ulong vendor, device;
759 ulong header_type;
Bin Meng4d8615c2015-07-19 00:20:04 +0800760 pci_dev_t bdf, end;
Simon Glassff3e0772015-03-05 12:25:25 -0700761 bool found_multi;
762 int ret;
763
764 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800765 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
766 PCI_MAX_PCI_FUNCTIONS - 1);
Yoshinori Sato6d9f5b02016-04-25 15:41:01 +0900767 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
Bin Meng4d8615c2015-07-19 00:20:04 +0800768 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700769 struct pci_child_platdata *pplat;
770 struct udevice *dev;
771 ulong class;
772
Bin Meng64e45f72018-08-03 01:14:37 -0700773 if (!PCI_FUNC(bdf))
774 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800775 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassff3e0772015-03-05 12:25:25 -0700776 continue;
Hou Zhiqiang2a87f7f2018-10-08 16:35:47 +0800777
Simon Glassff3e0772015-03-05 12:25:25 -0700778 /* Check only the first access, we don't expect problems */
Hou Zhiqiang2a87f7f2018-10-08 16:35:47 +0800779 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
780 PCI_SIZE_16);
Simon Glassff3e0772015-03-05 12:25:25 -0700781 if (ret)
782 goto error;
Hou Zhiqiang2a87f7f2018-10-08 16:35:47 +0800783
Simon Glassff3e0772015-03-05 12:25:25 -0700784 if (vendor == 0xffff || vendor == 0x0000)
785 continue;
786
Hou Zhiqiang2a87f7f2018-10-08 16:35:47 +0800787 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
788 &header_type, PCI_SIZE_8);
789
Bin Meng4d8615c2015-07-19 00:20:04 +0800790 if (!PCI_FUNC(bdf))
Simon Glassff3e0772015-03-05 12:25:25 -0700791 found_multi = header_type & 0x80;
792
793 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
Bin Meng4d8615c2015-07-19 00:20:04 +0800794 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
795 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassff3e0772015-03-05 12:25:25 -0700796 PCI_SIZE_16);
Bin Meng4d8615c2015-07-19 00:20:04 +0800797 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glassaba92962015-07-06 16:47:44 -0600798 PCI_SIZE_32);
799 class >>= 8;
Simon Glassff3e0772015-03-05 12:25:25 -0700800
801 /* Find this device in the device tree */
Bin Meng4d8615c2015-07-19 00:20:04 +0800802 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700803
Simon Glass8bd42522015-11-29 13:18:09 -0700804 /* If nothing in the device tree, bind a device */
Simon Glassff3e0772015-03-05 12:25:25 -0700805 if (ret == -ENODEV) {
Simon Glassaba92962015-07-06 16:47:44 -0600806 struct pci_device_id find_id;
807 ulong val;
Simon Glassff3e0772015-03-05 12:25:25 -0700808
Simon Glassaba92962015-07-06 16:47:44 -0600809 memset(&find_id, '\0', sizeof(find_id));
810 find_id.vendor = vendor;
811 find_id.device = device;
812 find_id.class = class;
813 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng4d8615c2015-07-19 00:20:04 +0800814 pci_bus_read_config(bus, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600815 PCI_SUBSYSTEM_VENDOR_ID,
816 &val, PCI_SIZE_32);
817 find_id.subvendor = val & 0xffff;
818 find_id.subdevice = val >> 16;
819 }
Bin Meng4d8615c2015-07-19 00:20:04 +0800820 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600821 &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700822 }
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600823 if (ret == -EPERM)
824 continue;
825 else if (ret)
Simon Glassff3e0772015-03-05 12:25:25 -0700826 return ret;
827
828 /* Update the platform data */
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600829 pplat = dev_get_parent_platdata(dev);
830 pplat->devfn = PCI_MASK_BUS(bdf);
831 pplat->vendor = vendor;
832 pplat->device = device;
833 pplat->class = class;
Simon Glassff3e0772015-03-05 12:25:25 -0700834 }
835
836 return 0;
837error:
838 printf("Cannot read bus configuration: %d\n", ret);
839
840 return ret;
841}
842
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700843static void decode_regions(struct pci_controller *hose, ofnode parent_node,
844 ofnode node)
Simon Glassff3e0772015-03-05 12:25:25 -0700845{
846 int pci_addr_cells, addr_cells, size_cells;
847 int cells_per_record;
848 const u32 *prop;
849 int len;
850 int i;
851
Masahiro Yamada61e51ba2017-06-22 16:54:05 +0900852 prop = ofnode_get_property(node, "ranges", &len);
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700853 if (!prop) {
854 debug("%s: Cannot decode regions\n", __func__);
855 return;
856 }
857
Simon Glass878d68c2017-06-12 06:21:31 -0600858 pci_addr_cells = ofnode_read_simple_addr_cells(node);
859 addr_cells = ofnode_read_simple_addr_cells(parent_node);
860 size_cells = ofnode_read_simple_size_cells(node);
Simon Glassff3e0772015-03-05 12:25:25 -0700861
862 /* PCI addresses are always 3-cells */
863 len /= sizeof(u32);
864 cells_per_record = pci_addr_cells + addr_cells + size_cells;
865 hose->region_count = 0;
866 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
867 cells_per_record);
868 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
869 u64 pci_addr, addr, size;
870 int space_code;
871 u32 flags;
872 int type;
Simon Glass9526d832015-11-19 20:26:58 -0700873 int pos;
Simon Glassff3e0772015-03-05 12:25:25 -0700874
875 if (len < cells_per_record)
876 break;
877 flags = fdt32_to_cpu(prop[0]);
878 space_code = (flags >> 24) & 3;
879 pci_addr = fdtdec_get_number(prop + 1, 2);
880 prop += pci_addr_cells;
881 addr = fdtdec_get_number(prop, addr_cells);
882 prop += addr_cells;
883 size = fdtdec_get_number(prop, size_cells);
884 prop += size_cells;
Masahiro Yamadadee37fc2018-08-06 20:47:40 +0900885 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
886 __func__, hose->region_count, pci_addr, addr, size, space_code);
Simon Glassff3e0772015-03-05 12:25:25 -0700887 if (space_code & 2) {
888 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
889 PCI_REGION_MEM;
890 } else if (space_code & 1) {
891 type = PCI_REGION_IO;
892 } else {
893 continue;
894 }
Tuomas Tynkkynen52ba9072018-05-14 18:47:50 +0300895
896 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
897 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
898 debug(" - beyond the 32-bit boundary, ignoring\n");
899 continue;
900 }
901
Simon Glass9526d832015-11-19 20:26:58 -0700902 pos = -1;
903 for (i = 0; i < hose->region_count; i++) {
904 if (hose->regions[i].flags == type)
905 pos = i;
906 }
907 if (pos == -1)
908 pos = hose->region_count++;
909 debug(" - type=%d, pos=%d\n", type, pos);
910 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassff3e0772015-03-05 12:25:25 -0700911 }
912
913 /* Add a region for our local memory */
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100914#ifdef CONFIG_NR_DRAM_BANKS
915 bd_t *bd = gd->bd;
916
Bin Meng1eaf7802018-03-27 00:46:05 -0700917 if (!bd)
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700918 return;
Bin Meng1eaf7802018-03-27 00:46:05 -0700919
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100920 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
921 if (bd->bi_dram[i].size) {
922 pci_set_region(hose->regions + hose->region_count++,
923 bd->bi_dram[i].start,
924 bd->bi_dram[i].start,
925 bd->bi_dram[i].size,
926 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
927 }
928 }
929#else
930 phys_addr_t base = 0, size;
931
Simon Glass2084c5a2015-11-19 20:26:57 -0700932 size = gd->ram_size;
933#ifdef CONFIG_SYS_SDRAM_BASE
934 base = CONFIG_SYS_SDRAM_BASE;
935#endif
936 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
937 size = gd->pci_ram_top - base;
Bin Mengee1109b2018-03-27 00:46:06 -0700938 if (size)
939 pci_set_region(hose->regions + hose->region_count++, base,
940 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100941#endif
Simon Glassff3e0772015-03-05 12:25:25 -0700942
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700943 return;
Simon Glassff3e0772015-03-05 12:25:25 -0700944}
945
946static int pci_uclass_pre_probe(struct udevice *bus)
947{
948 struct pci_controller *hose;
Simon Glassff3e0772015-03-05 12:25:25 -0700949
950 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
951 bus->parent->name);
952 hose = bus->uclass_priv;
953
954 /* For bridges, use the top-level PCI controller */
Paul Burton65f62b12016-09-08 07:47:32 +0100955 if (!device_is_on_pci_bus(bus)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700956 hose->ctlr = bus;
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700957 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
Simon Glassff3e0772015-03-05 12:25:25 -0700958 } else {
959 struct pci_controller *parent_hose;
960
961 parent_hose = dev_get_uclass_priv(bus->parent);
962 hose->ctlr = parent_hose->bus;
963 }
964 hose->bus = bus;
965 hose->first_busno = bus->seq;
966 hose->last_busno = bus->seq;
967
968 return 0;
969}
970
971static int pci_uclass_post_probe(struct udevice *bus)
972{
973 int ret;
974
Simon Glassff3e0772015-03-05 12:25:25 -0700975 debug("%s: probing bus %d\n", __func__, bus->seq);
976 ret = pci_bind_bus_devices(bus);
977 if (ret)
978 return ret;
979
980#ifdef CONFIG_PCI_PNP
981 ret = pci_auto_config_devices(bus);
Simon Glass4d214552015-09-08 17:52:47 -0600982 if (ret < 0)
983 return ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700984#endif
985
Bin Meng348b7442015-08-20 06:40:23 -0700986#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
987 /*
988 * Per Intel FSP specification, we should call FSP notify API to
989 * inform FSP that PCI enumeration has been done so that FSP will
990 * do any necessary initialization as required by the chipset's
991 * BIOS Writer's Guide (BWG).
992 *
993 * Unfortunately we have to put this call here as with driver model,
994 * the enumeration is all done on a lazy basis as needed, so until
995 * something is touched on PCI it won't happen.
996 *
997 * Note we only call this 1) after U-Boot is relocated, and 2)
998 * root bus has finished probing.
999 */
Simon Glass4d214552015-09-08 17:52:47 -06001000 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
Bin Meng348b7442015-08-20 06:40:23 -07001001 ret = fsp_init_phase_pci();
Simon Glass4d214552015-09-08 17:52:47 -06001002 if (ret)
1003 return ret;
1004 }
Bin Meng348b7442015-08-20 06:40:23 -07001005#endif
1006
Simon Glass4d214552015-09-08 17:52:47 -06001007 return 0;
Simon Glassff3e0772015-03-05 12:25:25 -07001008}
1009
1010static int pci_uclass_child_post_bind(struct udevice *dev)
1011{
1012 struct pci_child_platdata *pplat;
1013 struct fdt_pci_addr addr;
1014 int ret;
1015
Simon Glassbf501592017-05-18 20:09:51 -06001016 if (!dev_of_valid(dev))
Simon Glassff3e0772015-03-05 12:25:25 -07001017 return 0;
1018
Simon Glassff3e0772015-03-05 12:25:25 -07001019 pplat = dev_get_parent_platdata(dev);
Bin Meng1f6b08b2018-08-03 01:14:36 -07001020
1021 /* Extract vendor id and device id if available */
1022 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1023
1024 /* Extract the devfn from fdt_pci_addr */
Simon Glassbf501592017-05-18 20:09:51 -06001025 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
1026 &addr);
Simon Glassff3e0772015-03-05 12:25:25 -07001027 if (ret) {
1028 if (ret != -ENOENT)
1029 return -EINVAL;
1030 } else {
Bin Mengdce54dd2015-08-20 06:40:26 -07001031 pplat->devfn = addr.phys_hi & 0xff00;
Simon Glassff3e0772015-03-05 12:25:25 -07001032 }
1033
1034 return 0;
1035}
1036
Bin Meng4d8615c2015-07-19 00:20:04 +08001037static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1038 uint offset, ulong *valuep,
1039 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001040{
1041 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001042
1043 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1044}
1045
Bin Meng4d8615c2015-07-19 00:20:04 +08001046static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1047 uint offset, ulong value,
1048 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001049{
1050 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001051
1052 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1053}
1054
Simon Glass76c3fbc2015-08-10 07:05:04 -06001055static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1056{
1057 struct udevice *dev;
1058 int ret = 0;
1059
1060 /*
1061 * Scan through all the PCI controllers. On x86 there will only be one
1062 * but that is not necessarily true on other hardware.
1063 */
1064 do {
1065 device_find_first_child(bus, &dev);
1066 if (dev) {
1067 *devp = dev;
1068 return 0;
1069 }
1070 ret = uclass_next_device(&bus);
1071 if (ret)
1072 return ret;
1073 } while (bus);
1074
1075 return 0;
1076}
1077
1078int pci_find_next_device(struct udevice **devp)
1079{
1080 struct udevice *child = *devp;
1081 struct udevice *bus = child->parent;
1082 int ret;
1083
1084 /* First try all the siblings */
1085 *devp = NULL;
1086 while (child) {
1087 device_find_next_child(&child);
1088 if (child) {
1089 *devp = child;
1090 return 0;
1091 }
1092 }
1093
1094 /* We ran out of siblings. Try the next bus */
1095 ret = uclass_next_device(&bus);
1096 if (ret)
1097 return ret;
1098
1099 return bus ? skip_to_next_device(bus, devp) : 0;
1100}
1101
1102int pci_find_first_device(struct udevice **devp)
1103{
1104 struct udevice *bus;
1105 int ret;
1106
1107 *devp = NULL;
1108 ret = uclass_first_device(UCLASS_PCI, &bus);
1109 if (ret)
1110 return ret;
1111
1112 return skip_to_next_device(bus, devp);
1113}
1114
Simon Glass9289db62015-11-19 20:26:59 -07001115ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1116{
1117 switch (size) {
1118 case PCI_SIZE_8:
1119 return (value >> ((offset & 3) * 8)) & 0xff;
1120 case PCI_SIZE_16:
1121 return (value >> ((offset & 2) * 8)) & 0xffff;
1122 default:
1123 return value;
1124 }
1125}
1126
1127ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1128 enum pci_size_t size)
1129{
1130 uint off_mask;
1131 uint val_mask, shift;
1132 ulong ldata, mask;
1133
1134 switch (size) {
1135 case PCI_SIZE_8:
1136 off_mask = 3;
1137 val_mask = 0xff;
1138 break;
1139 case PCI_SIZE_16:
1140 off_mask = 2;
1141 val_mask = 0xffff;
1142 break;
1143 default:
1144 return value;
1145 }
1146 shift = (offset & off_mask) * 8;
1147 ldata = (value & val_mask) << shift;
1148 mask = val_mask << shift;
1149 value = (old & ~mask) | ldata;
1150
1151 return value;
1152}
1153
Simon Glassf9260332015-11-19 20:27:01 -07001154int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1155 struct pci_region **memp, struct pci_region **prefp)
1156{
1157 struct udevice *bus = pci_get_controller(dev);
1158 struct pci_controller *hose = dev_get_uclass_priv(bus);
1159 int i;
1160
1161 *iop = NULL;
1162 *memp = NULL;
1163 *prefp = NULL;
1164 for (i = 0; i < hose->region_count; i++) {
1165 switch (hose->regions[i].flags) {
1166 case PCI_REGION_IO:
1167 if (!*iop || (*iop)->size < hose->regions[i].size)
1168 *iop = hose->regions + i;
1169 break;
1170 case PCI_REGION_MEM:
1171 if (!*memp || (*memp)->size < hose->regions[i].size)
1172 *memp = hose->regions + i;
1173 break;
1174 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1175 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1176 *prefp = hose->regions + i;
1177 break;
1178 }
1179 }
1180
1181 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1182}
1183
Simon Glassbab17cf2015-11-29 13:17:53 -07001184u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1185{
1186 u32 addr;
1187 int bar;
1188
1189 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1190 dm_pci_read_config32(dev, bar, &addr);
1191 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1192 return addr & PCI_BASE_ADDRESS_IO_MASK;
1193 else
1194 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1195}
1196
Simon Glass9d731c82016-01-18 20:19:15 -07001197void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1198{
1199 int bar;
1200
1201 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1202 dm_pci_write_config32(dev, bar, addr);
1203}
1204
Simon Glass21d1fe72015-11-29 13:18:03 -07001205static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1206 pci_addr_t bus_addr, unsigned long flags,
1207 unsigned long skip_mask, phys_addr_t *pa)
1208{
1209 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1210 struct pci_region *res;
1211 int i;
1212
Christian Gmeiner6f95d892018-06-10 06:25:06 -07001213 if (hose->region_count == 0) {
1214 *pa = bus_addr;
1215 return 0;
1216 }
1217
Simon Glass21d1fe72015-11-29 13:18:03 -07001218 for (i = 0; i < hose->region_count; i++) {
1219 res = &hose->regions[i];
1220
1221 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1222 continue;
1223
1224 if (res->flags & skip_mask)
1225 continue;
1226
1227 if (bus_addr >= res->bus_start &&
1228 (bus_addr - res->bus_start) < res->size) {
1229 *pa = (bus_addr - res->bus_start + res->phys_start);
1230 return 0;
1231 }
1232 }
1233
1234 return 1;
1235}
1236
1237phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1238 unsigned long flags)
1239{
1240 phys_addr_t phys_addr = 0;
1241 struct udevice *ctlr;
1242 int ret;
1243
1244 /* The root controller has the region information */
1245 ctlr = pci_get_controller(dev);
1246
1247 /*
1248 * if PCI_REGION_MEM is set we do a two pass search with preference
1249 * on matches that don't have PCI_REGION_SYS_MEMORY set
1250 */
1251 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1252 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1253 flags, PCI_REGION_SYS_MEMORY,
1254 &phys_addr);
1255 if (!ret)
1256 return phys_addr;
1257 }
1258
1259 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1260
1261 if (ret)
1262 puts("pci_hose_bus_to_phys: invalid physical address\n");
1263
1264 return phys_addr;
1265}
1266
1267int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1268 unsigned long flags, unsigned long skip_mask,
1269 pci_addr_t *ba)
1270{
1271 struct pci_region *res;
1272 struct udevice *ctlr;
1273 pci_addr_t bus_addr;
1274 int i;
1275 struct pci_controller *hose;
1276
1277 /* The root controller has the region information */
1278 ctlr = pci_get_controller(dev);
1279 hose = dev_get_uclass_priv(ctlr);
1280
Christian Gmeiner6f95d892018-06-10 06:25:06 -07001281 if (hose->region_count == 0) {
1282 *ba = phys_addr;
1283 return 0;
1284 }
1285
Simon Glass21d1fe72015-11-29 13:18:03 -07001286 for (i = 0; i < hose->region_count; i++) {
1287 res = &hose->regions[i];
1288
1289 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1290 continue;
1291
1292 if (res->flags & skip_mask)
1293 continue;
1294
1295 bus_addr = phys_addr - res->phys_start + res->bus_start;
1296
1297 if (bus_addr >= res->bus_start &&
1298 (bus_addr - res->bus_start) < res->size) {
1299 *ba = bus_addr;
1300 return 0;
1301 }
1302 }
1303
1304 return 1;
1305}
1306
1307pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1308 unsigned long flags)
1309{
1310 pci_addr_t bus_addr = 0;
1311 int ret;
1312
1313 /*
1314 * if PCI_REGION_MEM is set we do a two pass search with preference
1315 * on matches that don't have PCI_REGION_SYS_MEMORY set
1316 */
1317 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1318 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1319 PCI_REGION_SYS_MEMORY, &bus_addr);
1320 if (!ret)
1321 return bus_addr;
1322 }
1323
1324 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1325
1326 if (ret)
1327 puts("pci_hose_phys_to_bus: invalid physical address\n");
1328
1329 return bus_addr;
1330}
1331
1332void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1333{
1334 pci_addr_t pci_bus_addr;
1335 u32 bar_response;
1336
1337 /* read BAR address */
1338 dm_pci_read_config32(dev, bar, &bar_response);
1339 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1340
1341 /*
1342 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1343 * isn't actualy used on any platform because u-boot assumes a static
1344 * linear mapping. In the future, this could read the BAR size
1345 * and pass that as the size if needed.
1346 */
1347 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1348}
1349
Bin Menga8c5f8d2018-10-15 02:21:21 -07001350static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
Bin Mengdac01fd2018-08-03 01:14:52 -07001351{
Bin Mengdac01fd2018-08-03 01:14:52 -07001352 int ttl = PCI_FIND_CAP_TTL;
1353 u8 id;
1354 u16 ent;
Bin Mengdac01fd2018-08-03 01:14:52 -07001355
1356 dm_pci_read_config8(dev, pos, &pos);
Bin Menga8c5f8d2018-10-15 02:21:21 -07001357
Bin Mengdac01fd2018-08-03 01:14:52 -07001358 while (ttl--) {
1359 if (pos < PCI_STD_HEADER_SIZEOF)
1360 break;
1361 pos &= ~3;
1362 dm_pci_read_config16(dev, pos, &ent);
1363
1364 id = ent & 0xff;
1365 if (id == 0xff)
1366 break;
1367 if (id == cap)
1368 return pos;
1369 pos = (ent >> 8);
1370 }
1371
1372 return 0;
1373}
1374
Bin Menga8c5f8d2018-10-15 02:21:21 -07001375int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1376{
1377 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1378 cap);
1379}
1380
1381int dm_pci_find_capability(struct udevice *dev, int cap)
1382{
1383 u16 status;
1384 u8 header_type;
1385 u8 pos;
1386
1387 dm_pci_read_config16(dev, PCI_STATUS, &status);
1388 if (!(status & PCI_STATUS_CAP_LIST))
1389 return 0;
1390
1391 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1392 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1393 pos = PCI_CB_CAPABILITY_LIST;
1394 else
1395 pos = PCI_CAPABILITY_LIST;
1396
1397 return _dm_pci_find_next_capability(dev, pos, cap);
1398}
1399
1400int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
Bin Mengdac01fd2018-08-03 01:14:52 -07001401{
1402 u32 header;
1403 int ttl;
1404 int pos = PCI_CFG_SPACE_SIZE;
1405
1406 /* minimum 8 bytes per capability */
1407 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1408
Bin Menga8c5f8d2018-10-15 02:21:21 -07001409 if (start)
1410 pos = start;
1411
Bin Mengdac01fd2018-08-03 01:14:52 -07001412 dm_pci_read_config32(dev, pos, &header);
1413 /*
1414 * If we have no capabilities, this is indicated by cap ID,
1415 * cap version and next pointer all being 0.
1416 */
1417 if (header == 0)
1418 return 0;
1419
1420 while (ttl--) {
1421 if (PCI_EXT_CAP_ID(header) == cap)
1422 return pos;
1423
1424 pos = PCI_EXT_CAP_NEXT(header);
1425 if (pos < PCI_CFG_SPACE_SIZE)
1426 break;
1427
1428 dm_pci_read_config32(dev, pos, &header);
1429 }
1430
1431 return 0;
1432}
1433
Bin Menga8c5f8d2018-10-15 02:21:21 -07001434int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1435{
1436 return dm_pci_find_next_ext_capability(dev, 0, cap);
1437}
1438
Simon Glassff3e0772015-03-05 12:25:25 -07001439UCLASS_DRIVER(pci) = {
1440 .id = UCLASS_PCI,
1441 .name = "pci",
Simon Glass2bb02e42015-05-10 21:08:06 -06001442 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glass91195482016-07-05 17:10:10 -06001443 .post_bind = dm_scan_fdt_dev,
Simon Glassff3e0772015-03-05 12:25:25 -07001444 .pre_probe = pci_uclass_pre_probe,
1445 .post_probe = pci_uclass_post_probe,
1446 .child_post_bind = pci_uclass_child_post_bind,
1447 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1448 .per_child_platdata_auto_alloc_size =
1449 sizeof(struct pci_child_platdata),
1450};
1451
1452static const struct dm_pci_ops pci_bridge_ops = {
1453 .read_config = pci_bridge_read_config,
1454 .write_config = pci_bridge_write_config,
1455};
1456
1457static const struct udevice_id pci_bridge_ids[] = {
1458 { .compatible = "pci-bridge" },
1459 { }
1460};
1461
1462U_BOOT_DRIVER(pci_bridge_drv) = {
1463 .name = "pci_bridge_drv",
1464 .id = UCLASS_PCI,
1465 .of_match = pci_bridge_ids,
1466 .ops = &pci_bridge_ops,
1467};
1468
1469UCLASS_DRIVER(pci_generic) = {
1470 .id = UCLASS_PCI_GENERIC,
1471 .name = "pci_generic",
1472};
1473
1474static const struct udevice_id pci_generic_ids[] = {
1475 { .compatible = "pci-generic" },
1476 { }
1477};
1478
1479U_BOOT_DRIVER(pci_generic_drv) = {
1480 .name = "pci_generic_drv",
1481 .id = UCLASS_PCI_GENERIC,
1482 .of_match = pci_generic_ids,
1483};
Stephen Warrene578b922016-01-26 11:10:11 -07001484
1485void pci_init(void)
1486{
1487 struct udevice *bus;
1488
1489 /*
1490 * Enumerate all known controller devices. Enumeration has the side-
1491 * effect of probing them, so PCIe devices will be enumerated too.
1492 */
1493 for (uclass_first_device(UCLASS_PCI, &bus);
1494 bus;
1495 uclass_next_device(&bus)) {
1496 ;
1497 }
1498}