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Graeme Russc620c012008-12-07 10:28:57 +11001/*
2 * (C) Copyright 2008
3 * Graeme Russ, graeme.russ@gmail.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/ic/sc520.h>
27
28#ifdef CONFIG_HW_WATCHDOG
29#include <watchdog.h>
30#endif
31
32#include "hardware.h"
33
34DECLARE_GLOBAL_DATA_PTR;
35
36#undef SC520_CDP_DEBUG
37
38#ifdef SC520_CDP_DEBUG
39#define PRINTF(fmt,args...) printf (fmt ,##args)
40#else
41#define PRINTF(fmt,args...)
42#endif
43
44unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
45
46void init_sc520_enet (void)
47{
48 /* Set CPU Speed to 100MHz */
Graeme Russed7a1b62009-08-23 12:59:56 +100049 sc520_mmcr->cpuctl = 0x01;
Graeme Russc620c012008-12-07 10:28:57 +110050
51 /* wait at least one millisecond */
52 asm("movl $0x2000,%%ecx\n"
Graeme Russcfb3a732009-08-23 12:59:46 +100053 "0: pushl %%ecx\n"
Graeme Russc620c012008-12-07 10:28:57 +110054 "popl %%ecx\n"
Graeme Russcfb3a732009-08-23 12:59:46 +100055 "loop 0b\n": : : "ecx");
Graeme Russc620c012008-12-07 10:28:57 +110056
57 /* turn on the SDRAM write buffer */
Graeme Russed7a1b62009-08-23 12:59:56 +100058 sc520_mmcr->dbctl = 0x11;
Graeme Russc620c012008-12-07 10:28:57 +110059
60 /* turn on the cache and disable write through */
61 asm("movl %%cr0, %%eax\n"
62 "andl $0x9fffffff, %%eax\n"
63 "movl %%eax, %%cr0\n" : : : "eax");
64}
65
66/*
67 * Miscellaneous platform dependent initializations
68 */
Graeme Russ1c409bc2009-11-24 20:04:21 +110069int board_early_init_f(void)
Graeme Russc620c012008-12-07 10:28:57 +110070{
71 init_sc520_enet();
72
Graeme Russed7a1b62009-08-23 12:59:56 +100073 sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */
74 sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */
75 sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */
76 sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */
77 sc520_mmcr->gprdoff = 0x01; /* GP Read offset */
78 sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */
79 sc520_mmcr->gpwroff = 0x01; /* GP Write offset */
Graeme Russc620c012008-12-07 10:28:57 +110080
Graeme Russed7a1b62009-08-23 12:59:56 +100081 sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */
82 sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */
83 sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */
84 sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */
85 sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */
86 sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */
87 sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */
Graeme Russc620c012008-12-07 10:28:57 +110088
Graeme Russed7a1b62009-08-23 12:59:56 +100089 sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
90 sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
91 sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
92 sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
93 sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */
94 sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
95 sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
96 sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */
97 sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */
98 sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */
99 sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */
100 sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */
101/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */
102/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
Graeme Russc620c012008-12-07 10:28:57 +1100103
104 /* Disable Watchdog */
Graeme Russed7a1b62009-08-23 12:59:56 +1000105 sc520_mmcr->wdtmrctl = 0x3333;
106 sc520_mmcr->wdtmrctl = 0xcccc;
107 sc520_mmcr->wdtmrctl = 0x0000;
Graeme Russc620c012008-12-07 10:28:57 +1100108
109 /* Chip Select Configuration */
Graeme Russed7a1b62009-08-23 12:59:56 +1000110 sc520_mmcr->bootcsctl = 0x0033;
111 sc520_mmcr->romcs1ctl = 0x0615;
112 sc520_mmcr->romcs2ctl = 0x0615;
Graeme Russc620c012008-12-07 10:28:57 +1100113
Graeme Russed7a1b62009-08-23 12:59:56 +1000114 sc520_mmcr->adddecctl = 0x02;
115 sc520_mmcr->uart1ctl = 0x07;
116 sc520_mmcr->sysarbctl = 0x06;
117 sc520_mmcr->sysarbmenb = 0x0003;
Graeme Russc620c012008-12-07 10:28:57 +1100118
Graeme Russ1c409bc2009-11-24 20:04:21 +1100119 return 0;
120}
121
122int board_early_init_r(void)
123{
124 /* CPU Speed to 100MHz */
125 gd->cpu_clk = 100000000;
126
Graeme Russc620c012008-12-07 10:28:57 +1100127 /* Crystal is 33.000MHz */
128 gd->bus_clk = 33000000;
129
130 return 0;
131}
132
133int dram_init(void)
134{
135 init_sc520_dram();
136 return 0;
137}
138
139void show_boot_progress(int val)
140{
141 uchar led_mask;
142
143 led_mask = 0x00;
144
145 if (val < 0)
146 led_mask |= LED_ERR_BITMASK;
147
148 led_mask |= (uchar)(val & 0x001f);
149 outb(led_mask, LED_LATCH_ADDRESS);
150}
151
152
153int last_stage_init(void)
154{
155 int minor;
156 int major;
157
158 major = minor = 0;
159
160 printf("Serck Controls eNET\n");
161
162 return 0;
163}
164
165ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
166{
167 if (banknum == 0) { /* non-CFI boot flash */
168 info->portwidth = FLASH_CFI_8BIT;
169 info->chipwidth = FLASH_CFI_BY8;
170 info->interface = FLASH_CFI_X8;
171 return 1;
172 } else
173 return 0;
174}