blob: 27dabaa9651c7291b052a100a981a9a148623f19 [file] [log] [blame]
Graeme Russc620c012008-12-07 10:28:57 +11001/*
2 * (C) Copyright 2008
3 * Graeme Russ, graeme.russ@gmail.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/ic/sc520.h>
27
28#ifdef CONFIG_HW_WATCHDOG
29#include <watchdog.h>
30#endif
31
32#include "hardware.h"
33
34DECLARE_GLOBAL_DATA_PTR;
35
36#undef SC520_CDP_DEBUG
37
38#ifdef SC520_CDP_DEBUG
39#define PRINTF(fmt,args...) printf (fmt ,##args)
40#else
41#define PRINTF(fmt,args...)
42#endif
43
44unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
45
46void init_sc520_enet (void)
47{
48 /* Set CPU Speed to 100MHz */
49 write_mmcr_byte(SC520_CPUCTL, 1);
50 gd->cpu_clk = 100000000;
51
52 /* wait at least one millisecond */
53 asm("movl $0x2000,%%ecx\n"
Graeme Russcfb3a732009-08-23 12:59:46 +100054 "0: pushl %%ecx\n"
Graeme Russc620c012008-12-07 10:28:57 +110055 "popl %%ecx\n"
Graeme Russcfb3a732009-08-23 12:59:46 +100056 "loop 0b\n": : : "ecx");
Graeme Russc620c012008-12-07 10:28:57 +110057
58 /* turn on the SDRAM write buffer */
59 write_mmcr_byte(SC520_DBCTL, 0x11);
60
61 /* turn on the cache and disable write through */
62 asm("movl %%cr0, %%eax\n"
63 "andl $0x9fffffff, %%eax\n"
64 "movl %%eax, %%cr0\n" : : : "eax");
65}
66
67/*
68 * Miscellaneous platform dependent initializations
69 */
70int board_init(void)
71{
72 init_sc520_enet();
73
74 write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */
75 write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */
76 write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */
77 write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */
78 write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */
79 write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */
80 write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */
81
82 write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */
83 write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */
84 write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */
85 write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */
86 write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */
87 write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */
88 write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */
89
90 write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
91 write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
92 write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
93 write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
94 write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */
95 write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
96 write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
97 write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */
98 write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */
99 write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
100 write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */
101 write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */
102/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */
103/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
104
105 /* Disable Watchdog */
106 write_mmcr_word(0x0cb0, 0x3333);
107 write_mmcr_word(0x0cb0, 0xcccc);
108 write_mmcr_word(0x0cb0, 0x0000);
109
110 /* Chip Select Configuration */
111 write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
112 write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
113 write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
114
115 write_mmcr_byte(SC520_ADDDECCTL, 0x02);
116 write_mmcr_byte(SC520_UART1CTL, 0x07);
117 write_mmcr_byte(SC520_SYSARBCTL,0x06);
118 write_mmcr_word(SC520_SYSARBMENB, 0x0003);
119
120 /* Crystal is 33.000MHz */
121 gd->bus_clk = 33000000;
122
123 return 0;
124}
125
126int dram_init(void)
127{
128 init_sc520_dram();
129 return 0;
130}
131
132void show_boot_progress(int val)
133{
134 uchar led_mask;
135
136 led_mask = 0x00;
137
138 if (val < 0)
139 led_mask |= LED_ERR_BITMASK;
140
141 led_mask |= (uchar)(val & 0x001f);
142 outb(led_mask, LED_LATCH_ADDRESS);
143}
144
145
146int last_stage_init(void)
147{
148 int minor;
149 int major;
150
151 major = minor = 0;
152
153 printf("Serck Controls eNET\n");
154
155 return 0;
156}
157
158ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
159{
160 if (banknum == 0) { /* non-CFI boot flash */
161 info->portwidth = FLASH_CFI_8BIT;
162 info->chipwidth = FLASH_CFI_BY8;
163 info->interface = FLASH_CFI_X8;
164 return 1;
165 } else
166 return 0;
167}