Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <assert.h> |
| 32 | #include <bl_common.h> |
| 33 | #include <context_mgmt.h> |
| 34 | #include <errno.h> |
| 35 | #include <interrupt_mgmt.h> |
| 36 | #include <platform.h> |
| 37 | #include <stdio.h> |
| 38 | |
| 39 | /******************************************************************************* |
| 40 | * Local structure and corresponding array to keep track of the state of the |
| 41 | * registered interrupt handlers for each interrupt type. |
| 42 | * The field descriptions are: |
| 43 | * |
| 44 | * 'flags' : Bit[0], Routing model for this interrupt type when execution is |
| 45 | * not in EL3 in the secure state. '1' implies that this |
| 46 | * interrupt will be routed to EL3. '0' implies that this |
| 47 | * interrupt will be routed to the current exception level. |
| 48 | * |
| 49 | * Bit[1], Routing model for this interrupt type when execution is |
| 50 | * not in EL3 in the non-secure state. '1' implies that this |
| 51 | * interrupt will be routed to EL3. '0' implies that this |
| 52 | * interrupt will be routed to the current exception level. |
| 53 | * |
| 54 | * All other bits are reserved and SBZ. |
| 55 | * |
| 56 | * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the |
| 57 | * value of the SCR_EL3.IRQ or FIQ bit for each security state. |
| 58 | * There are two instances of this field corresponding to the |
| 59 | * two security states. |
| 60 | ******************************************************************************/ |
| 61 | typedef struct intr_type_desc { |
| 62 | interrupt_type_handler_t handler; |
| 63 | uint32_t flags; |
| 64 | uint32_t scr_el3[2]; |
| 65 | } intr_type_desc_t; |
| 66 | |
| 67 | static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * This function validates the interrupt type. EL3 interrupts are currently not |
| 71 | * supported. |
| 72 | ******************************************************************************/ |
| 73 | static int32_t validate_interrupt_type(uint32_t type) |
| 74 | { |
| 75 | if (type == INTR_TYPE_EL3) |
| 76 | return -ENOTSUP; |
| 77 | |
| 78 | if (type != INTR_TYPE_S_EL1 && type != INTR_TYPE_NS) |
| 79 | return -EINVAL; |
| 80 | |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | /******************************************************************************* |
| 85 | * This function validates the routing model for this type of interrupt |
| 86 | ******************************************************************************/ |
| 87 | static int32_t validate_routing_model(uint32_t type, uint32_t flags) |
| 88 | { |
| 89 | flags >>= INTR_RM_FLAGS_SHIFT; |
| 90 | flags &= INTR_RM_FLAGS_MASK; |
| 91 | |
| 92 | if (type == INTR_TYPE_S_EL1) |
| 93 | return validate_sel1_interrupt_rm(flags); |
| 94 | |
| 95 | if (type == INTR_TYPE_NS) |
| 96 | return validate_ns_interrupt_rm(flags); |
| 97 | |
| 98 | return -EINVAL; |
| 99 | } |
| 100 | |
| 101 | /******************************************************************************* |
| 102 | * This function returns the cached copy of the SCR_EL3 which contains the |
| 103 | * routing model (expressed through the IRQ and FIQ bits) for a security state |
| 104 | * which was stored through a call to 'set_routing_model()' earlier. |
| 105 | ******************************************************************************/ |
| 106 | uint32_t get_scr_el3_from_routing_model(uint32_t security_state) |
| 107 | { |
| 108 | uint32_t scr_el3; |
| 109 | |
| 110 | assert(sec_state_is_valid(security_state)); |
| 111 | scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; |
| 112 | scr_el3 |= intr_type_descs[INTR_TYPE_S_EL1].scr_el3[security_state]; |
| 113 | scr_el3 |= intr_type_descs[INTR_TYPE_EL3].scr_el3[security_state]; |
| 114 | return scr_el3; |
| 115 | } |
| 116 | |
| 117 | /******************************************************************************* |
| 118 | * This function uses the 'interrupt_type_flags' parameter to obtain the value |
| 119 | * of the trap bit (IRQ/FIQ) in the SCR_EL3 for a security state for this |
| 120 | * interrupt type. It uses it to update the SCR_EL3 in the cpu context and the |
| 121 | * 'intr_type_desc' for that security state. |
| 122 | ******************************************************************************/ |
| 123 | static void set_scr_el3_from_rm(uint32_t type, |
| 124 | uint32_t interrupt_type_flags, |
| 125 | uint32_t security_state) |
| 126 | { |
| 127 | uint32_t flag, bit_pos; |
| 128 | |
| 129 | flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); |
| 130 | bit_pos = plat_interrupt_type_to_line(type, security_state); |
| 131 | intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; |
| 132 | cm_write_scr_el3_bit(security_state, bit_pos, flag); |
| 133 | } |
| 134 | |
| 135 | /******************************************************************************* |
| 136 | * This function validates the routing model specified in the 'flags' and |
| 137 | * updates internal data structures to reflect the new routing model. It also |
| 138 | * updates the copy of SCR_EL3 for each security state with the new routing |
| 139 | * model in the 'cpu_context' structure for this cpu. |
| 140 | ******************************************************************************/ |
| 141 | int32_t set_routing_model(uint32_t type, uint32_t flags) |
| 142 | { |
| 143 | int32_t rc; |
| 144 | |
| 145 | rc = validate_interrupt_type(type); |
| 146 | if (rc) |
| 147 | return rc; |
| 148 | |
| 149 | rc = validate_routing_model(type, flags); |
| 150 | if (rc) |
| 151 | return rc; |
| 152 | |
| 153 | /* Update the routing model in internal data structures */ |
| 154 | intr_type_descs[type].flags = flags; |
| 155 | set_scr_el3_from_rm(type, flags, SECURE); |
| 156 | set_scr_el3_from_rm(type, flags, NON_SECURE); |
| 157 | |
| 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | /****************************************************************************** |
| 162 | * This function disables the routing model of interrupt 'type' from the |
| 163 | * specified 'security_state' on the local core. The disable is in effect |
| 164 | * till the core powers down or till the next enable for that interrupt |
| 165 | * type. |
| 166 | *****************************************************************************/ |
| 167 | int disable_intr_rm_local(uint32_t type, uint32_t security_state) |
| 168 | { |
| 169 | uint32_t bit_pos, flag; |
| 170 | |
| 171 | assert(intr_type_descs[type].handler); |
| 172 | |
| 173 | flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state); |
| 174 | |
| 175 | bit_pos = plat_interrupt_type_to_line(type, security_state); |
| 176 | cm_write_scr_el3_bit(security_state, bit_pos, flag); |
| 177 | |
| 178 | return 0; |
| 179 | } |
| 180 | |
| 181 | /****************************************************************************** |
| 182 | * This function enables the routing model of interrupt 'type' from the |
| 183 | * specified 'security_state' on the local core. |
| 184 | *****************************************************************************/ |
| 185 | int enable_intr_rm_local(uint32_t type, uint32_t security_state) |
| 186 | { |
| 187 | uint32_t bit_pos, flag; |
| 188 | |
| 189 | assert(intr_type_descs[type].handler); |
| 190 | |
| 191 | flag = get_interrupt_rm_flag(intr_type_descs[type].flags, |
| 192 | security_state); |
| 193 | |
| 194 | bit_pos = plat_interrupt_type_to_line(type, security_state); |
| 195 | cm_write_scr_el3_bit(security_state, bit_pos, flag); |
| 196 | |
| 197 | return 0; |
| 198 | } |
| 199 | |
| 200 | /******************************************************************************* |
| 201 | * This function registers a handler for the 'type' of interrupt specified. It |
| 202 | * also validates the routing model specified in the 'flags' for this type of |
| 203 | * interrupt. |
| 204 | ******************************************************************************/ |
| 205 | int32_t register_interrupt_type_handler(uint32_t type, |
| 206 | interrupt_type_handler_t handler, |
| 207 | uint32_t flags) |
| 208 | { |
| 209 | int32_t rc; |
| 210 | |
| 211 | /* Validate the 'handler' parameter */ |
| 212 | if (!handler) |
| 213 | return -EINVAL; |
| 214 | |
| 215 | /* Validate the 'flags' parameter */ |
| 216 | if (flags & INTR_TYPE_FLAGS_MASK) |
| 217 | return -EINVAL; |
| 218 | |
| 219 | /* Check if a handler has already been registered */ |
| 220 | if (intr_type_descs[type].handler) |
| 221 | return -EALREADY; |
| 222 | |
| 223 | rc = set_routing_model(type, flags); |
| 224 | if (rc) |
| 225 | return rc; |
| 226 | |
| 227 | /* Save the handler */ |
| 228 | intr_type_descs[type].handler = handler; |
| 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | /******************************************************************************* |
| 234 | * This function is called when an interrupt is generated and returns the |
| 235 | * handler for the interrupt type (if registered). It returns NULL if the |
| 236 | * interrupt type is not supported or its handler has not been registered. |
| 237 | ******************************************************************************/ |
| 238 | interrupt_type_handler_t get_interrupt_type_handler(uint32_t type) |
| 239 | { |
| 240 | if (validate_interrupt_type(type)) |
| 241 | return NULL; |
| 242 | |
| 243 | return intr_type_descs[type].handler; |
| 244 | } |
| 245 | |