| Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame] | 1 | //------------------------------------------------------------------------------
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| 2 | //
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| 3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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| 4 | //
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| 5 | // This program and the accompanying materials
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| 6 | // are licensed and made available under the terms and conditions of the BSD License
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| 7 | // which accompanies this distribution. The full text of the license may be found at
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| 8 | // http://opensource.org/licenses/bsd-license.php
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| 9 | //
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| 10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 | //
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| 13 | //------------------------------------------------------------------------------
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| 14 |
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| 15 | #include <AsmMacroIoLib.h>
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| 16 | #include <Library/PcdLib.h>
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| 17 | #include <AutoGen.h>
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| 18 | INCLUDE AsmMacroIoLib.inc
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| 19 |
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| 20 | IMPORT CEntryPoint
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| 21 | EXPORT _ModuleEntryPoint
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| 22 |
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| 23 | PRESERVE8
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| 24 | AREA ModuleEntryPoint, CODE, READONLY
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| 25 |
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| 26 |
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| 27 | _ModuleEntryPoint
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| 28 |
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| 29 | //Disable L2 cache
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| 30 | mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
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| 31 | bic r0, r0, #0x00000002 // disable L2 cache
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| 32 | mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
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| 33 |
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| 34 | //Enable Strict alignment checking & Instruction cache
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| 35 | mrc p15, 0, r0, c1, c0, 0
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| 36 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
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| 37 | bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
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| 38 | orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
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| 39 | orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
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| 40 | mcr p15, 0, r0, c1, c0, 0
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| 41 |
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| 42 | // Enable NEON register in case folks want to use them for optimizations (CopyMem)
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| 43 | mrc p15, 0, r0, c1, c0, 2
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| 44 | orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
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| 45 | mcr p15, 0, r0, c1, c0, 2
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| 46 | mov r0, #0x40000000 // Set EN bit in FPEXC
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| 47 | msr FPEXC,r0
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| 48 |
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| 49 | // Set CPU vectors to start of DRAM
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| 50 | LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
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| 51 | mcr p15, 0, r0, c12, c0, 0
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| 52 | isb // Sync changes to control registers
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| 53 |
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| 54 | // Fill vector table with branchs to current pc (jmp $)
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| 55 | ldr r1, ShouldNeverGetHere
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| 56 | movs r2, #0
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| 57 | FillVectors
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| 58 | str r1, [r0, r2]
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| 59 | adds r2, r2, #4
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| 60 | cmp r2, #32
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| 61 | bne FillVectors
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| 62 |
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| 63 | /* before we call C code, lets setup the stack pointer in internal RAM */
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| 64 | stack_pointer_setup
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| 65 |
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| 66 | //
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| 67 | // Set stack based on PCD values. Need to do it this way to make C code work
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| 68 | // when it runs from FLASH.
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| 69 | //
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| 70 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2
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| 71 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3
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| 72 | add r4, r2, r3
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| 73 |
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| 74 | //Enter SVC mode and set up SVC stack pointer
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| 75 | mov r5,#0x13|0x80|0x40
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| 76 | msr CPSR_c,r5
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| 77 | mov r13,r4
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| 78 |
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| 79 | // Call C entry point
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| 80 | LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1
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| 81 | LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory start arg0
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| 82 | blx CEntryPoint // Assume C code is thumb
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| 83 |
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| 84 | ShouldNeverGetHere
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| 85 | /* _CEntryPoint should never return */
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| 86 | b ShouldNeverGetHere
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| 87 |
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| 88 | END
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| 89 |
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