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gerrit.devboardsforandroid.linaro.org / device / linaro / hikey960 / 0e33772df9ca72fb5f6e3d9a9b9ee547997b1b66 / . / uefi / linaro-edk2 / EmbeddedPkg / Universal / MmcDxe / Mmc.h
blob: bdb0a1ca2e53e3b071b57708c0455eca9237ad9e [file] [log] [blame]
Vishal Bhoj82c80712015-12-15 21:13:33 +0530[diff] [blame]1/** @file
2 Main Header file for the MMC DXE driver
3
4 Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14**/
15
16#ifndef __MMC_H
17#define __MMC_H
18
19#include <Uefi.h>
20
21#include <Protocol/DiskIo.h>
22#include <Protocol/BlockIo.h>
23#include <Protocol/DevicePath.h>
24#include <Protocol/MmcHost.h>
25
26#include <Library/UefiLib.h>
27#include <Library/DebugLib.h>
28
29#define MMC_TRACE(txt) DEBUG((EFI_D_BLKIO, "MMC: " txt "\n"))
30
31#define MMC_IOBLOCKS_READ 0
32#define MMC_IOBLOCKS_WRITE 1
33
34#define MMC_OCR_POWERUP 0x80000000
35
36#define MMC_CSD_GET_CCC(Response) (Response[2] >> 20)
37#define MMC_CSD_GET_TRANSPEED(Response) (Response[3] & 0xFF)
38#define MMC_CSD_GET_READBLLEN(Response) ((Response[2] >> 16) & 0xF)
39#define MMC_CSD_GET_WRITEBLLEN(Response) ((Response[0] >> 22) & 0xF)
40#define MMC_CSD_GET_FILEFORMAT(Response) ((Response[0] >> 10) & 0x3)
41#define MMC_CSD_GET_FILEFORMATGRP(Response) ((Response[0] >> 15) & 0x1)
42#define MMC_CSD_GET_DEVICESIZE(csd) (((Response[1] >> 30) & 0x3) | ((Response[2] & 0x3FF) << 2))
43#define HC_MMC_CSD_GET_DEVICESIZE(Response) ((Response[1] >> 16) | ((Response[2] & 0x40) << 16));
44#define MMC_CSD_GET_DEVICESIZEMULT(csd) ((Response[1] >> 15) & 0x7)
45
46#define MMC_R0_READY_FOR_DATA (1 << 8)
47
48#define MMC_R0_CURRENTSTATE(Response) ((Response[0] >> 9) & 0xF)
49
50#define MMC_R0_STATE_IDLE 0
51#define MMC_R0_STATE_READY 1
52#define MMC_R0_STATE_IDENT 2
53#define MMC_R0_STATE_STDBY 3
54#define MMC_R0_STATE_TRAN 4
55#define MMC_R0_STATE_DATA 5
56
57typedef enum {
58 UNKNOWN_CARD,
59 MMC_CARD, //MMC card
60 MMC_CARD_HIGH, //MMC Card with High capacity
61 EMMC_CARD, //eMMC 4.41 card
62 SD_CARD, //SD 1.1 card
63 SD_CARD_2, //SD 2.0 or above standard card
64 SD_CARD_2_HIGH //SD 2.0 or above high capacity card
65} CARD_TYPE;
66
67typedef struct {
68 UINT32 Reserved0: 7; // 0
69 UINT32 V170_V195: 1; // 1.70V - 1.95V
70 UINT32 V200_V260: 7; // 2.00V - 2.60V
71 UINT32 V270_V360: 9; // 2.70V - 3.60V
72 UINT32 RESERVED_1: 5; // Reserved
73 UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
74 UINT32 PowerUp: 1; // This bit is set to LOW if the card has not finished the power up routine
75} OCR;
76
77/* For little endian CPU */
78typedef struct {
79 UINT8 SD_SPEC: 4; // SD Memory Card - Spec. Version [59:56]
80 UINT8 SCR_STRUCTURE: 4; // SCR Structure [63:60]
81 UINT8 SD_BUS_WIDTHS: 4; // DAT Bus widths supported [51:48]
82 UINT8 DATA_STAT_AFTER_ERASE: 1; // Data Status after erases [55]
83 UINT8 SD_SECURITY: 3; // CPRM Security Support [54:52]
84 UINT8 EX_SECURITY_1: 1; // Extended Security Support [43]
85 UINT8 SD_SPEC4: 1; // Spec. Version 4.00 or higher [42]
86 UINT8 RESERVED_1: 2; // Reserved [41:40]
87 UINT8 SD_SPEC3: 1; // Spec. Version 3.00 or higher [47]
88 UINT8 EX_SECURITY_2: 3; // Extended Security Support [46:44]
89 UINT8 CMD_SUPPORT: 4; // Command Support bits [35:32]
90 UINT8 RESERVED_2: 4; // Reserved [39:36]
91 UINT32 RESERVED_3; // Manufacturer Usage [31:0]
92} SCR;
93
94typedef struct {
95 UINT32 NOT_USED; // 1 [0:0]
96 UINT32 CRC; // CRC7 checksum [7:1]
97 UINT32 MDT; // Manufacturing date [19:8]
98 UINT32 RESERVED_1; // Reserved [23:20]
99 UINT32 PSN; // Product serial number [55:24]
100 UINT8 PRV; // Product revision [63:56]
101 UINT8 PNM[5]; // Product name [64:103]
102 UINT16 OID; // OEM/Application ID [119:104]
103 UINT8 MID; // Manufacturer ID [127:120]
104} CID;
105
106typedef struct {
107 UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
108 UINT8 CRC: 7; // CRC [7:1]
109
110 UINT8 RESERVED_1: 2; // Reserved [9:8]
111 UINT8 FILE_FORMAT: 2; // File format [11:10]
112 UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
113 UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
114 UINT8 COPY: 1; // Copy flag (OTP) [14:14]
115 UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
116
117 UINT16 RESERVED_2: 5; // Reserved [20:16]
118 UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
119 UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
120 UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
121 UINT16 RESERVED_3: 2; // Reserved [30:29]
122 UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
123
124 UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]
125 UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]
126 UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
127 UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
128 UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
129 UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
130 UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
131 UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
132 UINT32 C_SIZELow2: 2; // Device size [63:62]
133
134 UINT32 C_SIZEHigh10: 10;// Device size [73:64]
135 UINT32 RESERVED_4: 2; // Reserved [75:74]
136 UINT32 DSR_IMP: 1; // DSR implemented [76:76]
137 UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
138 UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
139 UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
140 UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
141 UINT32 CCC: 12;// Card command classes [95:84]
142
143 UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
144 UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
145 UINT8 TAAC ; // Data read access-time 1 [119:112]
146
147 UINT8 RESERVED_5: 2; // Reserved [121:120]
148 UINT8 SPEC_VERS: 4; // System specification version [125:122]
149 UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
150} CSD;
151
152typedef struct {
153 UINT8 RESERVED_1[16]; // Reserved [15:0]
154 UINT8 SECURE_REMOVAL_TYPE; // Secure Removal Type [16:16]
155 UINT8 PRODUCT_STATE_AWARENESS_ENABLEMENT; // Product state awareness enablement [17:17]
156 UINT8 MAX_PRE_LOADING_DATA_SIZE[4]; // MAX pre loading data size [21:18]
157 UINT8 PRE_LOADING_DATA_SIZE[4]; // Pre loading data size [25:22]
158 UINT8 FFU_STATUS; // FFU Status [26:26]
159 UINT8 RESERVED_2[2]; // Reserved [28:27]
160 UINT8 MODE_OPERATION_CODES; // Mode operation codes [29:29]
161 UINT8 MODE_CONFIG; // Mode config [30:30]
162 UINT8 RESERVED_3; // Reserved [31:31]
163 UINT8 FLUSH_CACHE; // Flushing of the cache [32:32]
164 UINT8 CACHE_CTRL; // Control to turn the cache ON/OFF [33:33]
165 UINT8 POWER_OFF_NOTIFICATION; // Power Off Notification [34:34]
166 UINT8 PACKED_FAILURE_INDEX; // Packed command failure index [35:35]
167 UINT8 PACKED_COMMAND_STATUS; // Packed command status [36:36]
168 UINT8 CONTEXT_CONF[15]; // Context configuration [51:37]
169 UINT8 EXT_PARTITIONS_ATTRIBUTE[2]; // Extended partitions attribute [53:52]
170 UINT8 EXCEPTION_EVENTS_STATUS[2]; // Exception events status [55:54]
171 UINT8 EXCEPTION_EVENTS_CTRL[2]; // Exception events control [57:56]
172 UINT8 DYNCAP_NEEDED; // Number of addressed group to be released [58:58]
173 UINT8 CLASS_6_CTRL; // Class 6 commands control [59:59]
174 UINT8 INI_TIMEOUT_EMU; // 1st initialization after disabling sector size emulation [60:60]
175 UINT8 DATA_SECTOR_SIZE; // Sector size [61:61]
176 UINT8 USE_NATIVE_SECTOR; // Sector size emulation [62:62]
177 UINT8 NATIVE_SECTOR_SIZE; // Native sector size [63:63]
178 UINT8 VENDOR_SPECIFIC_FIELD[64]; // Vendor specific fields [127:64]
179 UINT8 RESERVED_4[2]; // Reserved [129:128]
180 UINT8 PROGRAM_CID_CSD_DDR_SUPPORT; // Program CID/CSD in DDR mode support [130:130]
181 UINT8 PERIODIC_WAKEUP; // Periodic wake-up [131:131]
182 UINT8 TCASE_SUPPORT; // Package case temperature is controlled [132:132]
183 UINT8 PRODUCTION_STATE_AWARENESS; // Production state awareness [133:133]
184 UINT8 SEC_BAD_BLK_MGMNT; // Bad block management mode [134:134]
185 UINT8 RESERVED_5; // Reserved [135:135]
186 UINT8 ENH_START_ADDR[4]; // Enhanced user data start address [139:136]
187 UINT8 ENH_SIZE_MULT[3]; // Enhanced user data area size [142:140]
188 UINT8 GP_SIZE_MULT[12]; // General purpose partition size [154:143]
189 UINT8 PARTITION_SETTING_COMPLETED; // Partitioning setting [155:155]
190 UINT8 PARTITIONS_ATTRIBUTE; // Partitions attribute [156:156]
191 UINT8 MAX_ENH_SIZE_MULT[3]; // Max enhanced area size [159:157]
192 UINT8 PARTITIONING_SUPPORT; // Partitioning [160:160]
193 UINT8 HPI_MGMT; // HPI management [161:161]
194 UINT8 RST_N_FUNCTION; // H/W reset function [162:162]
195 UINT8 BKOPS_EN; // Enable background operations handshake [163:163]
196 UINT8 BKOPS_START; // Manually start background operations [164:164]
197 UINT8 SANITIZE_START; // Start sanitize operation [165:165]
198 UINT8 WR_REL_PARAM; // Write reliability parameter register [166:166]
199 UINT8 WR_REL_SET; // Write reliability setting register [167:167]
200 UINT8 RPMB_SIZE_MULT; // RPMB size [168:168]
201 UINT8 FW_CONFIG; // FW configuration [169:169]
202 UINT8 RESERVED_6; // Reserved [170:170]
203 UINT8 USER_WP; // User area write protection register [171:171]
204 UINT8 RESERVED_7; // Reserved [172:172]
205 UINT8 BOOT_WP; // Boot area write protection register [173:173]
206 UINT8 BOOT_WP_STATUS; // Boot write protection register [174:174]
207 UINT8 ERASE_GROUP_DEF; // High-density erase group definition [175:175]
208 UINT8 RESERVED_8; // Reserved [176:176]
209 UINT8 BOOT_BUS_CONDITIONS; // Boot bus conditions [177:177]
210 UINT8 BOOT_CONFIG_PROT; // Boot config protection [178:178]
211 UINT8 PARTITION_CONFIG; // Partition config [179:179]
212 UINT8 RESERVED_9; // Reserved [180:180]
213 UINT8 ERASED_MEM_CONT; // Erased memory content [181:181]
214 UINT8 RESERVED_10; // Reserved [182:182]
215 UINT8 BUS_WIDTH; // Bus width mode [183:183]
216 UINT8 RESERVED_11; // Reserved [184:184]
217 UINT8 HS_TIMING; // High-speed interface timing [185:185]
218 UINT8 RESERVED_12; // Reserved [186:186]
219 UINT8 POWER_CLASS; // Power class [187:187]
220 UINT8 RESERVED_13; // Reserved [188:188]
221 UINT8 CMD_SET_REV; // Command set revision [189:189]
222 UINT8 RESERVED_14; // Reserved [190:190]
223 UINT8 CMD_SET; // Command set [191:191]
224 UINT8 EXT_CSD_REV; // Extended CSD revision [192:192]
225 UINT8 RESERVED_15; // Reserved [193:193]
226 UINT8 CSD_STRUCTURE; // CSD Structure [194:194]
227 UINT8 RESERVED_16; // Reserved [195:195]
228 UINT8 DEVICE_TYPE; // Device type [196:196]
229 UINT8 DRIVER_STRENGTH; // I/O Driver strength [197:197]
230 UINT8 OUT_OF_INTERRUPT_TIME; // Out-of-interrupt busy timing [198:198]
231 UINT8 PARTITION_SWITCH_TIME; // Partition switching timing [199:199]
232 UINT8 PWR_CL_52_195; // Power class for 52MHz at 1.95V 1 R [200:200]
233 UINT8 PWR_CL_26_195; // Power class for 26MHz at 1.95V 1 R [201:201]
234 UINT8 PWR_CL_52_360; // Power class for 52MHz at 3.6V 1 R [202:202]
235 UINT8 PWR_CL_26_360; // Power class for 26MHz at 3.6V 1 R [203:203]
236 UINT8 RESERVED_17; // Reserved [204:204]
237 UINT8 MIN_PERF_R_4_26; // Minimum read performance for 4bit at 26MHz [205:205]
238 UINT8 MIN_PERF_W_4_26; // Minimum write performance for 4bit at 26MHz [206:206]
239 UINT8 MIN_PERF_R_8_26_4_52; // Minimum read performance for 8bit at 26MHz, for 4bit at 52MHz [207:207]
240 UINT8 MIN_PERF_W_8_26_4_52; // Minimum write performance for 8bit at 26MHz, for 4bit at 52MHz [208:208]
241 UINT8 MIN_PERF_R_8_52; // Minimum read performance for 8bit at 52MHz [209:209]
242 UINT8 MIN_PERF_W_8_52; // Minimum write performance for 8bit at 52MHz [210:210]
243 UINT8 RESERVED_18; // Reserved [211:211]
244 UINT32 SEC_COUNT; // Sector count [215:212]
245 UINT8 SLEEP_NOTIFICATION_TIME; // Sleep notification timout [216:216]
246 UINT8 S_A_TIMEOUT; // Sleep/awake timeout [217:217]
247 UINT8 PRODUCTION_STATE_AWARENESS_TIMEOUT; // Production state awareness timeout [218:218]
248 UINT8 S_C_VCCQ; // Sleep current (VCCQ) [219:219]
249 UINT8 S_C_VCC; // Sleep current (VCC) [220:220]
250 UINT8 HC_WP_GRP_SIZE; // High-capacity write protect group size [221:221]
251 UINT8 REL_WR_SEC_C; // Reliable write sector count [222:222]
252 UINT8 ERASE_TIMEOUT_MULT; // High-capacity erase timeout [223:223]
253 UINT8 HC_ERASE_GRP_SIZE; // High-capacity erase unit size [224:224]
254 UINT8 ACC_SIZE; // Access size [225:225]
255 UINT8 BOOT_SIZE_MULTI; // Boot partition size [226:226]
256 UINT8 RESERVED_19; // Reserved [227:227]
257 UINT8 BOOT_INFO; // Boot information [228:228]
258 UINT8 SEC_TRIM_MULT; // Secure TRIM Multiplier [229:229]
259 UINT8 SEC_ERASE_MULT; // Secure Erase Multiplier [230:230]
260 UINT8 SEC_FEATURE_SUPPORT; // Secure Feature Support [231:231]
261 UINT8 TRIM_MULT; // TRIM Multiplier [232:232]
262 UINT8 RESERVED_20; // Reserved [233:233]
263 UINT8 MIN_PREF_DDR_R_8_52; // Minimum read performance for 8bit at 52MHz in DDR mode [234:234]
264 UINT8 MIN_PREF_DDR_W_8_52; // Minimum write performance for 8bit at 52MHz in DDR mode [235:235]
265 UINT8 PWR_CL_200_130; // Power class for 200MHz at VCCQ=1.3V, VCC=3.6V [236:236]
266 UINT8 PWR_CL_200_195; // Power class for 200MHz at VCCQ=1.95V, VCC=3.6V [237:237]
267 UINT8 PWR_CL_DDR_52_195; // Power class for 52MHz, DDR at 1.95V [238:238]
268 UINT8 PWR_CL_DDR_52_360; // Power class for 52Mhz, DDR at 3.6V [239:239]
269 UINT8 RESERVED_21; // Reserved [240:240]
270 UINT8 INI_TIMEOUT_AP; // 1st initialization time after partitioning [241:241]
271 UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // Number of correctly programmed sectors [245:242]
272 UINT8 BKOPS_STATUS; // Background operations status [246:246]
273 UINT8 POWER_OFF_LONG_TIME; // Power off notification (long) timeout [247:247]
274 UINT8 GENERIC_CMD6_TIME; // Generic CMD6 timeout [248:248]
275 UINT8 CACHE_SIZE[4]; // Cache size [252:249]
276 UINT8 PWR_CL_DDR_200_360; // Power class for 200MHz, DDR at VCC=3.6V [253:253]
277 UINT8 FIRMWARE_VERSION[8]; // Firmware version [261:254]
278 UINT8 DEVICE_VERSION[2]; // Device version [263:262]
279 UINT8 OPTIMAL_TRIM_UNIT_SIZE; // Optimal trim unit size [264:264]
280 UINT8 OPTIMAL_WRITE_SIZE; // Optimal write size [265:265]
281 UINT8 OPTIMAL_READ_SIZE; // Optimal read size [266:266]
282 UINT8 PRE_EOL_INFO; // Pre EOL information [267:267]
283 UINT8 DEVICE_LIFE_TIME_EST_TYP_A; // Device life time estimation type A [268:268]
284 UINT8 DEVICE_LIFE_TIME_EST_TYP_B; // Device life time estimation type B [269:269]
285 UINT8 VENDOR_PROPRIETARY_HEALTH_REPORT[32]; // Vendor proprietary health report [301:270]
286 UINT8 NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED[4]; // Number of FW sectors correctly programmed [305:302]
287 UINT8 RESERVED_22[181]; // Reserved [486:306]
288 UINT8 FFU_ARG[4]; // FFU argument [490:487]
289 UINT8 OPERATION_CODE_TIMEOUT; // Operation codes timeout [491:491]
290 UINT8 FFU_FEATURES; // FFU features [492:492]
291 UINT8 SUPPORTED_MODES; // Supported modes [493:493]
292 UINT8 EXT_SUPPORT; // Extended partitions attribute support [494:494]
293 UINT8 LARGE_UNIT_SIZE_M1; // Large unit size [495:495]
294 UINT8 CONTEXT_CAPABILITIES; // Context management capabilities [496:496]
295 UINT8 TAG_RES_SIZE; // Tag resource size [497:497]
296 UINT8 TAG_UNIT_SIZE; // Tag unit size [498:498]
297 UINT8 DATA_TAG_SUPPORT; // Data tag support [499:499]
298 UINT8 MAX_PACKED_WRITES; // Max packed write commands [500:500]
299 UINT8 MAX_PACKED_READS; // Max packed read commands [501:501]
300 UINT8 BKOPS_SUPPORT; // Background operations support [502:502]
301 UINT8 HPI_FEATURES; // HPI features [503:503]
302 UINT8 S_CMD_SET; // Supported command sets [504:504]
303 UINT8 EXT_SECURITY_ERR; // Extended security commands error [505:505]
304 UINT8 RESERVED_23[6]; // Reserved [511:506]
305} ECSD;
306
307typedef struct {
308 UINT16 RCA;
309 CARD_TYPE CardType;
310 OCR OCRData;
311 CID CIDData;
312 CSD CSDData;
313 ECSD ECSDData; // MMC V4 extended card specific
314} CARD_INFO;
315
316typedef struct _MMC_HOST_INSTANCE {
317 UINTN Signature;
318 LIST_ENTRY Link;
319 EFI_HANDLE MmcHandle;
320 EFI_DEVICE_PATH_PROTOCOL *DevicePath;
321
322 MMC_STATE State;
323 EFI_BLOCK_IO_PROTOCOL BlockIo;
324 CARD_INFO CardInfo;
325 EFI_MMC_HOST_PROTOCOL *MmcHost;
326
327 BOOLEAN Initialized;
328} MMC_HOST_INSTANCE;
329
330#define MMC_HOST_INSTANCE_SIGNATURE SIGNATURE_32('m', 'm', 'c', 'h')
331#define MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS(a) CR (a, MMC_HOST_INSTANCE, BlockIo, MMC_HOST_INSTANCE_SIGNATURE)
332#define MMC_HOST_INSTANCE_FROM_LINK(a) CR (a, MMC_HOST_INSTANCE, Link, MMC_HOST_INSTANCE_SIGNATURE)
333
334
335EFI_STATUS
336EFIAPI
337MmcGetDriverName (
338 IN EFI_COMPONENT_NAME_PROTOCOL *This,
339 IN CHAR8 *Language,
340 OUT CHAR16 **DriverName
341 );
342
343EFI_STATUS
344EFIAPI
345MmcGetControllerName (
346 IN EFI_COMPONENT_NAME_PROTOCOL *This,
347 IN EFI_HANDLE ControllerHandle,
348 IN EFI_HANDLE ChildHandle OPTIONAL,
349 IN CHAR8 *Language,
350 OUT CHAR16 **ControllerName
351 );
352
353extern EFI_COMPONENT_NAME_PROTOCOL gMmcComponentName;
354extern EFI_COMPONENT_NAME2_PROTOCOL gMmcComponentName2;
355
356extern EFI_DRIVER_DIAGNOSTICS2_PROTOCOL gMmcDriverDiagnostics2;
357
358extern LIST_ENTRY mMmcHostPool;
359
360/**
361 Reset the block device.
362
363 This function implements EFI_BLOCK_IO_PROTOCOL.Reset().
364 It resets the block device hardware.
365 ExtendedVerification is ignored in this implementation.
366
367 @param This Indicates a pointer to the calling context.
368 @param ExtendedVerification Indicates that the driver may perform a more exhaustive
369 verification operation of the device during reset.
370
371 @retval EFI_SUCCESS The block device was reset.
372 @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be reset.
373
374**/
375EFI_STATUS
376EFIAPI
377MmcReset (
378 IN EFI_BLOCK_IO_PROTOCOL *This,
379 IN BOOLEAN ExtendedVerification
380 );
381
382/**
383 Reads the requested number of blocks from the device.
384
385 This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks().
386 It reads the requested number of blocks from the device.
387 All the blocks are read, or an error is returned.
388
389 @param This Indicates a pointer to the calling context.
390 @param MediaId The media ID that the read request is for.
391 @param Lba The starting logical block address to read from on the device.
392 @param BufferSize The size of the Buffer in bytes.
393 This must be a multiple of the intrinsic block size of the device.
394 @param Buffer A pointer to the destination buffer for the data. The caller is
395 responsible for either having implicit or explicit ownership of the buffer.
396
397 @retval EFI_SUCCESS The data was read correctly from the device.
398 @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation.
399 @retval EFI_NO_MEDIA There is no media in the device.
400 @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
401 @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic block size of the device.
402 @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
403 or the buffer is not on proper alignment.
404
405**/
406EFI_STATUS
407EFIAPI
408MmcReadBlocks (
409 IN EFI_BLOCK_IO_PROTOCOL *This,
410 IN UINT32 MediaId,
411 IN EFI_LBA Lba,
412 IN UINTN BufferSize,
413 OUT VOID *Buffer
414 );
415
416/**
417 Writes a specified number of blocks to the device.
418
419 This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks().
420 It writes a specified number of blocks to the device.
421 All blocks are written, or an error is returned.
422
423 @param This Indicates a pointer to the calling context.
424 @param MediaId The media ID that the write request is for.
425 @param Lba The starting logical block address to be written.
426 @param BufferSize The size of the Buffer in bytes.
427 This must be a multiple of the intrinsic block size of the device.
428 @param Buffer Pointer to the source buffer for the data.
429
430 @retval EFI_SUCCESS The data were written correctly to the device.
431 @retval EFI_WRITE_PROTECTED The device cannot be written to.
432 @retval EFI_NO_MEDIA There is no media in the device.
433 @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
434 @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the write operation.
435 @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic
436 block size of the device.
437 @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
438 or the buffer is not on proper alignment.
439
440**/
441EFI_STATUS
442EFIAPI
443MmcWriteBlocks (
444 IN EFI_BLOCK_IO_PROTOCOL *This,
445 IN UINT32 MediaId,
446 IN EFI_LBA Lba,
447 IN UINTN BufferSize,
448 IN VOID *Buffer
449 );
450
451/**
452 Flushes all modified data to a physical block device.
453
454 @param This Indicates a pointer to the calling context.
455
456 @retval EFI_SUCCESS All outstanding data were written correctly to the device.
457 @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data.
458 @retval EFI_NO_MEDIA There is no media in the device.
459
460**/
461EFI_STATUS
462EFIAPI
463MmcFlushBlocks (
464 IN EFI_BLOCK_IO_PROTOCOL *This
465 );
466
467EFI_STATUS
468MmcNotifyState (
469 IN MMC_HOST_INSTANCE *MmcHostInstance,
470 IN MMC_STATE State
471 );
472
473EFI_STATUS
474InitializeMmcDevice (
475 IN MMC_HOST_INSTANCE *MmcHost
476 );
477
478VOID
479EFIAPI
480CheckCardsCallback (
481 IN EFI_EVENT Event,
482 IN VOID *Context
483 );
484
485VOID
486PrintCSD (
487 IN UINT32* Csd
488 );
489
490VOID
491PrintRCA (
492 IN UINT32 Rca
493 );
494
495VOID
496PrintOCR (
497 IN UINT32 Ocr
498 );
499
500VOID
501PrintResponseR1 (
502 IN UINT32 Response
503 );
504
505VOID
506PrintCID (
507 IN UINT32* Cid
508 );
509
510#endif