Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame] | 1 | /** @file
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| 2 | Include file matches things in PI.
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| 3 |
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| 4 | Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
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| 5 | This program and the accompanying materials are licensed and made available under
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| 6 | the terms and conditions of the BSD License that accompanies this distribution.
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| 7 | The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php.
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 |
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| 13 | @par Revision Reference:
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| 14 | PI Version 1.3
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| 15 |
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| 16 | **/
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| 17 |
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| 18 | #ifndef __PI_I2C_H__
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| 19 | #define __PI_I2C_H__
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| 20 |
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| 21 | ///
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| 22 | /// A 10-bit slave address is or'ed with the following value enabling the
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| 23 | /// I2C protocol stack to address the duplicated address space between 0
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| 24 | // and 127 in 10-bit mode.
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| 25 | ///
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| 26 | #define I2C_ADDRESSING_10_BIT 0x80000000
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| 27 |
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| 28 | ///
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| 29 | /// I2C controller capabilities
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| 30 | ///
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| 31 | /// The EFI_I2C_CONTROLLER_CAPABILITIES specifies the capabilities of the
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| 32 | /// I2C host controller. The StructureSizeInBytes enables variations of
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| 33 | /// this structure to be identified if there is need to extend this
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| 34 | /// structure in the future.
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| 35 | ///
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| 36 | typedef struct {
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| 37 | ///
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| 38 | /// Length of this data structure in bytes
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| 39 | ///
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| 40 | UINT32 StructureSizeInBytes;
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| 41 |
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| 42 | ///
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| 43 | /// The maximum number of bytes the I2C host controller is able to
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| 44 | /// receive from the I2C bus.
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| 45 | ///
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| 46 | UINT32 MaximumReceiveBytes;
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| 47 |
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| 48 | ///
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| 49 | /// The maximum number of bytes the I2C host controller is able to send
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| 50 | /// on the I2C bus.
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| 51 | ///
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| 52 | UINT32 MaximumTransmitBytes;
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| 53 |
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| 54 | ///
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| 55 | /// The maximum number of bytes in the I2C bus transaction.
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| 56 | ///
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| 57 | UINT32 MaximumTotalBytes;
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| 58 | } EFI_I2C_CONTROLLER_CAPABILITIES;
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| 59 |
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| 60 | ///
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| 61 | /// I2C device description
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| 62 | ///
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| 63 | /// The EFI_I2C_ENUMERATE_PROTOCOL uses the EFI_I2C_DEVICE to describe
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| 64 | /// the platform specific details associated with an I2C device. This
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| 65 | /// description is passed to the I2C bus driver during enumeration where
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| 66 | /// it is made available to the third party I2C device driver via the
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| 67 | /// EFI_I2C_IO_PROTOCOL.
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| 68 | ///
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| 69 | typedef struct {
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| 70 | ///
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| 71 | /// Unique value assigned by the silicon manufacture or the third
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| 72 | /// party I2C driver writer for the I2C part. This value logically
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| 73 | /// combines both the manufacture name and the I2C part number into
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| 74 | /// a single value specified as a GUID.
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| 75 | ///
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| 76 | CONST EFI_GUID *DeviceGuid;
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| 77 |
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| 78 | ///
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| 79 | /// Unique ID of the I2C part within the system
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| 80 | ///
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| 81 | UINT32 DeviceIndex;
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| 82 |
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| 83 | ///
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| 84 | /// Hardware revision - ACPI _HRV value. See the Advanced
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| 85 | /// Configuration and Power Interface Specification, Revision 5.0
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| 86 | /// for the field format and the Plug and play support for I2C
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| 87 | /// web-page for restriction on values.
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| 88 | ///
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| 89 | /// http://www.acpi.info/spec.htm
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| 90 | /// http://msdn.microsoft.com/en-us/library/windows/hardware/jj131711(v=vs.85).aspx
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| 91 | ///
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| 92 | UINT32 HardwareRevision;
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| 93 |
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| 94 | ///
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| 95 | /// I2C bus configuration for the I2C device
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| 96 | ///
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| 97 | UINT32 I2cBusConfiguration;
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| 98 |
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| 99 | ///
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| 100 | /// Number of slave addresses for the I2C device.
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| 101 | ///
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| 102 | UINT32 SlaveAddressCount;
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| 103 |
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| 104 | ///
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| 105 | /// Pointer to the array of slave addresses for the I2C device.
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| 106 | ///
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| 107 | CONST UINT32 *SlaveAddressArray;
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| 108 | } EFI_I2C_DEVICE;
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| 109 |
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| 110 | ///
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| 111 | /// Define the I2C flags
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| 112 | ///
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| 113 | /// I2C read operation when set
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| 114 | #define I2C_FLAG_READ 0x00000001
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| 115 |
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| 116 | ///
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| 117 | /// Define the flags for SMBus operation
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| 118 | ///
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| 119 | /// The following flags are also present in only the first I2C operation
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| 120 | /// and are ignored when present in other operations. These flags
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| 121 | /// describe a particular SMB transaction as shown in the following table.
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| 122 | ///
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| 123 |
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| 124 | /// SMBus operation
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| 125 | #define I2C_FLAG_SMBUS_OPERATION 0x00010000
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| 126 |
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| 127 | /// SMBus block operation
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| 128 | /// The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update
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| 129 | /// the LengthInBytes field of the operation in the request packet with
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| 130 | /// the actual number of bytes read or written. These values are only
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| 131 | /// valid when the entire I2C transaction is successful.
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| 132 | /// This flag also changes the LengthInBytes meaning to be: A maximum
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| 133 | /// of LengthInBytes is to be read from the device. The first byte
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| 134 | /// read contains the number of bytes remaining to be read, plus an
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| 135 | /// optional PEC value.
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| 136 | #define I2C_FLAG_SMBUS_BLOCK 0x00020000
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| 137 |
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| 138 | /// SMBus process call operation
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| 139 | #define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000
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| 140 |
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| 141 | /// SMBus use packet error code (PEC)
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| 142 | /// Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit
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| 143 | /// to indicate that the PEC value was checked by the hardware and is
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| 144 | /// not appended to the returned read data.
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| 145 | ///
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| 146 | #define I2C_FLAG_SMBUS_PEC 0x00080000
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| 147 |
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| 148 | //----------------------------------------------------------------------
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| 149 | ///
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| 150 | /// QuickRead: OperationCount=1,
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| 151 | /// LengthInBytes=0, Flags=I2C_FLAG_READ
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| 152 | /// QuickWrite: OperationCount=1,
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| 153 | /// LengthInBytes=0, Flags=0
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| 154 | ///
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| 155 | ///
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| 156 | /// ReceiveByte: OperationCount=1,
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| 157 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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| 158 | /// | I2C_FLAG_READ
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| 159 | /// ReceiveByte+PEC: OperationCount=1,
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| 160 | /// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
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| 161 | /// | I2C_FLAG_READ
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| 162 | /// | I2C_FLAG_SMBUS_PEC
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| 163 | ///
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| 164 | ///
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| 165 | /// SendByte: OperationCount=1,
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| 166 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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| 167 | /// SendByte+PEC: OperationCount=1,
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| 168 | /// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
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| 169 | /// | I2C_FLAG_SMBUS_PEC
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| 170 | ///
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| 171 | ///
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| 172 | /// ReadDataByte: OperationCount=2,
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| 173 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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| 174 | /// LengthInBytes=1, Flags=I2C_FLAG_READ
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| 175 | /// ReadDataByte+PEC: OperationCount=2,
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| 176 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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| 177 | /// | I2C_FLAG_SMBUS_PEC
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| 178 | /// LengthInBytes=2, Flags=I2C_FLAG_READ
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| 179 | ///
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| 180 | ///
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| 181 | /// WriteDataByte: OperationCount=1,
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| 182 | /// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
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| 183 | /// WriteDataByte+PEC: OperationCount=1,
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| 184 | /// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
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| 185 | /// | I2C_FLAG_SMBUS_PEC
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| 186 | ///
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| 187 | ///
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| 188 | /// ReadDataWord: OperationCount=2,
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| 189 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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| 190 | /// LengthInBytes=2, Flags=I2C_FLAG_READ
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| 191 | /// ReadDataWord+PEC: OperationCount=2,
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| 192 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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| 193 | /// | I2C_FLAG_SMBUS_PEC
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| 194 | /// LengthInBytes=3, Flags=I2C_FLAG_READ
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| 195 | ///
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| 196 | ///
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| 197 | /// WriteDataWord: OperationCount=1,
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| 198 | /// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
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| 199 | /// WriteDataWord+PEC: OperationCount=1,
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| 200 | /// LengthInBytes=4, Flags=I2C_FLAG_SMBUS_OPERATION
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| 201 | /// | I2C_FLAG_SMBUS_PEC
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| 202 | ///
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| 203 | ///
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| 204 | /// ReadBlock: OperationCount=2,
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| 205 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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| 206 | /// | I2C_FLAG_SMBUS_BLOCK
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| 207 | /// LengthInBytes=33, Flags=I2C_FLAG_READ
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| 208 | /// ReadBlock+PEC: OperationCount=2,
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| 209 | /// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
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| 210 | /// | I2C_FLAG_SMBUS_BLOCK
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| 211 | /// | I2C_FLAG_SMBUS_PEC
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| 212 | /// LengthInBytes=34, Flags=I2C_FLAG_READ
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| 213 | ///
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| 214 | ///
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| 215 | /// WriteBlock: OperationCount=1,
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| 216 | /// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
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| 217 | /// | I2C_FLAG_SMBUS_BLOCK
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| 218 | /// WriteBlock+PEC: OperationCount=1,
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| 219 | /// LengthInBytes=N+3, Flags=I2C_FLAG_SMBUS_OPERATION
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| 220 | /// | I2C_FLAG_SMBUS_BLOCK
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| 221 | /// | I2C_FLAG_SMBUS_PEC
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| 222 | ///
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| 223 | ///
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| 224 | /// ProcessCall: OperationCount=2,
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| 225 | /// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
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| 226 | /// | I2C_FLAG_SMBUS_PROCESS_CALL
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| 227 | /// LengthInBytes=2, Flags=I2C_FLAG_READ
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| 228 | /// ProcessCall+PEC: OperationCount=2,
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| 229 | /// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
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| 230 | /// | I2C_FLAG_SMBUS_PROCESS_CALL
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| 231 | /// | I2C_FLAG_SMBUS_PEC
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| 232 | /// LengthInBytes=3, Flags=I2C_FLAG_READ
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| 233 | ///
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| 234 | ///
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| 235 | /// BlkProcessCall: OperationCount=2,
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| 236 | /// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
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| 237 | /// | I2C_FLAG_SMBUS_PROCESS_CALL
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| 238 | /// | I2C_FLAG_SMBUS_BLOCK
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| 239 | /// LengthInBytes=33, Flags=I2C_FLAG_READ
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| 240 | /// BlkProcessCall+PEC: OperationCount=2,
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| 241 | /// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
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| 242 | /// | I2C_FLAG_SMBUS_PROCESS_CALL
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| 243 | /// | I2C_FLAG_SMBUS_BLOCK
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| 244 | /// | I2C_FLAG_SMBUS_PEC
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| 245 | /// LengthInBytes=34, Flags=I2C_FLAG_READ
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| 246 | ///
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| 247 | //----------------------------------------------------------------------
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| 248 |
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| 249 | ///
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| 250 | /// I2C device operation
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| 251 | ///
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| 252 | /// The EFI_I2C_OPERATION describes a subset of an I2C transaction in which
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| 253 | /// the I2C controller is either sending or receiving bytes from the bus.
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| 254 | /// Some transactions will consist of a single operation while others will
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| 255 | /// be two or more.
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| 256 | ///
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| 257 | /// Note: Some I2C controllers do not support read or write ping (address
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| 258 | /// only) operation and will return EFI_UNSUPPORTED status when these
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| 259 | /// operations are requested.
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| 260 | ///
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| 261 | /// Note: I2C controllers which do not support complex transactions requiring
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| 262 | /// multiple repeated start bits return EFI_UNSUPPORTED without processing
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| 263 | /// any of the transaction.
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| 264 | ///
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| 265 | typedef struct {
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| 266 | ///
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| 267 | /// Flags to qualify the I2C operation.
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| 268 | ///
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| 269 | UINT32 Flags;
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| 270 |
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| 271 | ///
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| 272 | /// Number of bytes to send to or receive from the I2C device. A ping
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| 273 | /// (address only byte/bytes) is indicated by setting the LengthInBytes
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| 274 | /// to zero.
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| 275 | ///
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| 276 | UINT32 LengthInBytes;
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| 277 |
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| 278 | ///
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| 279 | /// Pointer to a buffer containing the data to send or to receive from
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| 280 | /// the I2C device. The Buffer must be at least LengthInBytes in size.
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| 281 | ///
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| 282 | UINT8 *Buffer;
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| 283 | } EFI_I2C_OPERATION;
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| 284 |
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| 285 | ///
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| 286 | /// I2C device request
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| 287 | ///
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| 288 | /// The EFI_I2C_REQUEST_PACKET describes a single I2C transaction. The
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| 289 | /// transaction starts with a start bit followed by the first operation
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| 290 | /// in the operation array. Subsequent operations are separated with
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| 291 | /// repeated start bits and the last operation is followed by a stop bit
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| 292 | /// which concludes the transaction. Each operation is described by one
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| 293 | /// of the elements in the Operation array.
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| 294 | ///
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| 295 | typedef struct {
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| 296 | ///
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| 297 | /// Number of elements in the operation array
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| 298 | ///
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| 299 | UINTN OperationCount;
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| 300 |
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| 301 | ///
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| 302 | /// Description of the I2C operation
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| 303 | ///
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| 304 | EFI_I2C_OPERATION Operation [1];
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| 305 | } EFI_I2C_REQUEST_PACKET;
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| 306 |
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| 307 | #endif // __PI_I2C_H__
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