Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame] | 1 | /** @file
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| 2 |
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| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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| 4 |
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| 5 | This program and the accompanying materials
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| 6 | are licensed and made available under the terms and conditions of the BSD License
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| 7 | which accompanies this distribution. The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 |
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| 13 | **/
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| 14 |
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| 15 | #ifndef __OMAP3530GPIO_H__
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| 16 | #define __OMAP3530GPIO_H__
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| 17 |
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| 18 | #define GPIO1_BASE (0x48310000)
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| 19 | #define GPIO2_BASE (0x49050000)
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| 20 | #define GPIO3_BASE (0x49052000)
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| 21 | #define GPIO4_BASE (0x49054000)
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| 22 | #define GPIO5_BASE (0x49056000)
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| 23 | #define GPIO6_BASE (0x49058000)
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| 24 |
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| 25 | #define GPIO_SYSCONFIG (0x0010)
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| 26 | #define GPIO_SYSSTATUS (0x0014)
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| 27 | #define GPIO_IRQSTATUS1 (0x0018)
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| 28 | #define GPIO_IRQENABLE1 (0x001C)
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| 29 | #define GPIO_WAKEUPENABLE (0x0020)
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| 30 | #define GPIO_IRQSTATUS2 (0x0028)
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| 31 | #define GPIO_IRQENABLE2 (0x002C)
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| 32 | #define GPIO_CTRL (0x0030)
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| 33 | #define GPIO_OE (0x0034)
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| 34 | #define GPIO_DATAIN (0x0038)
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| 35 | #define GPIO_DATAOUT (0x003C)
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| 36 | #define GPIO_LEVELDETECT0 (0x0040)
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| 37 | #define GPIO_LEVELDETECT1 (0x0044)
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| 38 | #define GPIO_RISINGDETECT (0x0048)
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| 39 | #define GPIO_FALLINGDETECT (0x004C)
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| 40 | #define GPIO_DEBOUNCENABLE (0x0050)
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| 41 | #define GPIO_DEBOUNCINGTIME (0x0054)
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| 42 | #define GPIO_CLEARIRQENABLE1 (0x0060)
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| 43 | #define GPIO_SETIRQENABLE1 (0x0064)
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| 44 | #define GPIO_CLEARIRQENABLE2 (0x0070)
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| 45 | #define GPIO_SETIRQENABLE2 (0x0074)
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| 46 | #define GPIO_CLEARWKUENA (0x0080)
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| 47 | #define GPIO_SETWKUENA (0x0084)
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| 48 | #define GPIO_CLEARDATAOUT (0x0090)
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| 49 | #define GPIO_SETDATAOUT (0x0094)
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| 50 |
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| 51 | #define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
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| 52 | #define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
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| 53 | #define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3
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| 54 | #define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
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| 55 | #define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2
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| 56 | #define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
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| 57 | #define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
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| 58 | #define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1
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| 59 | #define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
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| 60 | #define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1
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| 61 | #define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0
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| 62 | #define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
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| 63 | #define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0
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| 64 |
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| 65 | #define GPIO_SYSSTATUS_RESETDONE_MASK BIT0
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| 66 | #define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
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| 67 | #define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0
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| 68 |
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| 69 | #define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
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| 70 | #define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
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| 71 | #define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x))
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| 72 | #define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x))
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| 73 |
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| 74 | #define GPIO_IRQENABLE_MASK(x) (1UL << (x))
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| 75 | #define GPIO_IRQENABLE_DISABLE(x) (0UL << (x))
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| 76 | #define GPIO_IRQENABLE_ENABLE(x) (1UL << (x))
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| 77 |
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| 78 | #define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x))
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| 79 | #define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x))
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| 80 | #define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x))
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| 81 |
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| 82 | #define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
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| 83 | #define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
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| 84 | #define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1
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| 85 | #define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
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| 86 | #define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
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| 87 | #define GPIO_CTRL_DISABLEMODULE_MASK BIT0
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| 88 | #define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
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| 89 | #define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0
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| 90 |
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| 91 | #define GPIO_OE_MASK(x) (1UL << (x))
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| 92 | #define GPIO_OE_OUTPUT(x) (0UL << (x))
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| 93 | #define GPIO_OE_INPUT(x) (1UL << (x))
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| 94 |
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| 95 | #define GPIO_DATAIN_MASK(x) (1UL << (x))
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| 96 |
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| 97 | #define GPIO_DATAOUT_MASK(x) (1UL << (x))
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| 98 |
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| 99 | #define GPIO_LEVELDETECT_MASK(x) (1UL << (x))
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| 100 | #define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x))
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| 101 | #define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x))
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| 102 |
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| 103 | #define GPIO_RISINGDETECT_MASK(x) (1UL << (x))
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| 104 | #define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x))
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| 105 | #define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x))
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| 106 |
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| 107 | #define GPIO_FALLINGDETECT_MASK(x) (1UL << (x))
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| 108 | #define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x))
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| 109 | #define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x))
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| 110 |
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| 111 | #define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x))
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| 112 | #define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x))
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| 113 | #define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x))
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| 114 |
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| 115 | #define GPIO_DEBOUNCINGTIME_MASK (0xFF)
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| 116 | #define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)
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| 117 |
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| 118 | #define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x))
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| 119 |
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| 120 | #define GPIO_SETIRQENABLE_BIT(x) (1UL << (x))
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| 121 |
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| 122 | #define GPIO_CLEARWKUENA_BIT(x) (1UL << (x))
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| 123 |
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| 124 | #define GPIO_SETWKUENA_BIT(x) (1UL << (x))
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| 125 |
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| 126 | #define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x))
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| 127 |
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| 128 | #define GPIO_SETDATAOUT_BIT(x) (1UL << (x))
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| 129 |
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| 130 | #endif // __OMAP3530GPIO_H__
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| 131 |
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