blob: d45cb4b85222293ed6d7b897588275e93276c25e [file] [log] [blame]
Niranjan Yadla19336af2018-04-19 12:19:27 -07001/*******************************************************************************
2* Copyright (C) 2018 Cadence Design Systems, Inc.
3*
4* Permission is hereby granted, free of charge, to any person obtaining
5* a copy of this software and associated documentation files (the
6* "Software"), to use this Software with Cadence processor cores only and
7* not with any other processors and platforms, subject to
8* the following conditions:
9*
10* The above copyright notice and this permission notice shall be included
11* in all copies or substantial portions of the Software.
12*
13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
15* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
16* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
17* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
18* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
19* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20
21******************************************************************************/
22#include <xtensa/xtruntime.h>
23#include <xtensa/config/specreg.h>
24
25extern const unsigned char Xthal_have_ccount;
26extern const unsigned char Xthal_num_ccompare;
27extern void xthal_set_ccompare(int n, unsigned value);
28extern unsigned xthal_get_ccompare(int n);
29
30/*--------------------------------------------*/
31#include <xtensa/config/core.h>
32#define TIMER_INTERVAL 0x1000
33
34#define TIMER_INT_MASK (1 << XCHAL_TIMER0_INTERRUPT)
35#define TIMER2_INT_MASK (1 << XCHAL_TIMER1_INTERRUPT)
36#define TWO_TIMERS_INT_MASK ( TIMER_INT_MASK + TIMER2_INT_MASK )
37#define _XTSTR(x) # x
38#define XTSTR(x) _XTSTR(x)
39
40static __inline__ int read_ccount()
41{
42 unsigned int ccount;
43 __asm__ __volatile__ (
44 "rsr %0, "XTSTR(CCOUNT)
45 : "=a" (ccount)
46 );
47 return ccount;
48}
49
50static __inline__ int read_ccompare0()
51{
52 unsigned int ccompare0;
53 __asm__ __volatile__ (
54 "rsr %0, "XTSTR(CCOMPARE_0)
55 : "=a" (ccompare0)
56 );
57 return ccompare0;
58}
59
60static __inline__ int read_ccompare1()
61{
62 unsigned int ccompare1;
63 __asm__ __volatile__ (
64 "rsr %0, "XTSTR(CCOMPARE_1)
65 : "=a" (ccompare1)
66 );
67 return ccompare1;
68}
69
70static __inline__ unsigned int read_intenable()
71{
72 unsigned int intenable;
73 __asm__ __volatile__ (
74 "rsr %0, "XTSTR(INTENABLE)
75 : "=a" (intenable)
76 );
77 return intenable;
78}
79
80static __inline__ void set_ccompare1(int val)
81{
82 __asm__ __volatile__ (
83 "wsr %0, "XTSTR(CCOMPARE_1)"\n\t"
84 "isync\n\t"
85 :
86 : "a" (val)
87 );
88}
89
90static __inline__ void set_ccompare0(int val)
91{
92 __asm__ __volatile__ (
93 "wsr %0, "XTSTR(CCOMPARE_0)"\n\t"
94 "isync\n\t"
95 :
96 : "a" (val)
97 );
98}
99
100/*---------------------------------------------------*/
101
102static __inline__ void set_ccount(int val)
103{
104 __asm__ __volatile__ (
105 "wsr %0, ccount\n"
106 "isync\n"
107 :
108 : "a" (val)
109 );
110}
111