| Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame^] | 1 | /** @file
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| 2 | *
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| 3 | * Copyright (c) 2013-2014, ARM Limited. All rights reserved.
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| 4 | *
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| 5 | * This program and the accompanying materials
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| 6 | * are licensed and made available under the terms and conditions of the BSD
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| 7 | * License which accompanies this distribution. The full text of the license
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| 8 | * may be found at http://opensource.org/licenses/bsd-license.php
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| 9 | *
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| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 | *
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| 13 | **/
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| 14 | #ifndef __GENERIC_WATCHDOG_H__
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| 15 | #define __GENERIC_WATCHDOG_H__
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| 16 |
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| 17 | // Refresh Frame:
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| 18 | #define GENERIC_WDOG_REFRESH_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogRefreshBase) + 0x000)
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| 19 |
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| 20 | // Control Frame:
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| 21 | #define GENERIC_WDOG_CONTROL_STATUS_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x000)
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| 22 | #define GENERIC_WDOG_OFFSET_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x008)
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| 23 | #define GENERIC_WDOG_COMPARE_VALUE_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x010)
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| 24 |
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| 25 | // Values of bit 0 of the Control/Status Register
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| 26 | #define GENERIC_WDOG_ENABLED 1
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| 27 | #define GENERIC_WDOG_DISABLED 0
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| 28 |
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| 29 | #endif // __GENERIC_WATCHDOG_H__
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