| Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | * |
| 3 | * Copyright (c) 2014, Linaro Limited. All rights reserved. |
| 4 | * Copyright (c) 2014, Hisilicon Limited. All rights reserved. |
| 5 | * |
| 6 | * This program and the accompanying materials |
| 7 | * are licensed and made available under the terms and conditions of the BSD License |
| 8 | * which accompanies this distribution. The full text of the license may be found at |
| 9 | * http://opensource.org/licenses/bsd-license.php |
| 10 | * |
| 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. |
| 13 | * |
| 14 | **/ |
| 15 | |
| 16 | |
| 17 | #ifndef __DWMMC_H__ |
| 18 | #define __DWMMC_H__ |
| 19 | |
| 20 | #include <Protocol/EmbeddedGpio.h> |
| 21 | |
| 22 | // DW MMC Registers |
| 23 | #define DWMMC_CTRL ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x000) |
| 24 | #define DWMMC_PWREN ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x004) |
| 25 | #define DWMMC_CLKDIV ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x008) |
| 26 | #define DWMMC_CLKSRC ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x00c) |
| 27 | #define DWMMC_CLKENA ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x010) |
| 28 | #define DWMMC_TMOUT ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x014) |
| 29 | #define DWMMC_CTYPE ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x018) |
| 30 | #define DWMMC_BLKSIZ ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x01c) |
| 31 | #define DWMMC_BYTCNT ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x020) |
| 32 | #define DWMMC_INTMASK ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x024) |
| 33 | #define DWMMC_CMDARG ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x028) |
| 34 | #define DWMMC_CMD ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x02c) |
| 35 | #define DWMMC_RESP0 ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x030) |
| 36 | #define DWMMC_RESP1 ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x034) |
| 37 | #define DWMMC_RESP2 ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x038) |
| 38 | #define DWMMC_RESP3 ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x03c) |
| 39 | #define DWMMC_RINTSTS ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x044) |
| 40 | #define DWMMC_STATUS ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x048) |
| 41 | #define DWMMC_FIFOTH ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x04c) |
| 42 | #define DWMMC_DEBNCE ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x064) |
| 43 | #define DWMMC_UHSREG ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x074) |
| 44 | #define DWMMC_BMOD ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x080) |
| 45 | #define DWMMC_DBADDR ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x088) |
| 46 | #define DWMMC_IDSTS ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x08c) |
| 47 | #define DWMMC_IDINTEN ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x090) |
| 48 | #define DWMMC_DSCADDR ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x094) |
| 49 | #define DWMMC_BUFADDR ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0x098) |
| 50 | #define DWMMC_CARDTHRCTL ((UINT32)PcdGet32 (PcdDwMmcBaseAddress) + 0X100) |
| 51 | |
| 52 | #define CMD_UPDATE_CLK 0x80202000 |
| 53 | #define CMD_START_BIT (1 << 31) |
| 54 | |
| 55 | #define MMC_8BIT_MODE (1 << 16) |
| 56 | |
| 57 | #define BIT_CMD_RESPONSE_EXPECT (1 << 6) |
| 58 | #define BIT_CMD_LONG_RESPONSE (1 << 7) |
| 59 | #define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8) |
| 60 | #define BIT_CMD_DATA_EXPECTED (1 << 9) |
| 61 | #define BIT_CMD_READ (0 << 10) |
| 62 | #define BIT_CMD_WRITE (1 << 10) |
| 63 | #define BIT_CMD_BLOCK_TRANSFER (0 << 11) |
| 64 | #define BIT_CMD_STREAM_TRANSFER (1 << 11) |
| 65 | #define BIT_CMD_SEND_AUTO_STOP (1 << 12) |
| 66 | #define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) |
| 67 | #define BIT_CMD_STOP_ABORT_CMD (1 << 14) |
| 68 | #define BIT_CMD_SEND_INIT (1 << 15) |
| 69 | #define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21) |
| 70 | #define BIT_CMD_READ_CEATA_DEVICE (1 << 22) |
| 71 | #define BIT_CMD_CCS_EXPECTED (1 << 23) |
| 72 | #define BIT_CMD_ENABLE_BOOT (1 << 24) |
| 73 | #define BIT_CMD_EXPECT_BOOT_ACK (1 << 25) |
| 74 | #define BIT_CMD_DISABLE_BOOT (1 << 26) |
| 75 | #define BIT_CMD_MANDATORY_BOOT (0 << 27) |
| 76 | #define BIT_CMD_ALTERNATE_BOOT (1 << 27) |
| 77 | #define BIT_CMD_VOLT_SWITCH (1 << 28) |
| 78 | #define BIT_CMD_USE_HOLD_REG (1 << 29) |
| 79 | #define BIT_CMD_START (1 << 31) |
| 80 | |
| 81 | #define DWMMC_INT_EBE (1 << 15) /* End-bit Err */ |
| 82 | #define DWMMC_INT_SBE (1 << 13) /* Start-bit Err */ |
| 83 | #define DWMMC_INT_HLE (1 << 12) /* Hardware-lock Err */ |
| 84 | #define DWMMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */ |
| 85 | #define DWMMC_INT_DRT (1 << 9) /* Data timeout */ |
| 86 | #define DWMMC_INT_RTO (1 << 8) /* Response timeout */ |
| 87 | #define DWMMC_INT_DCRC (1 << 7) /* Data CRC err */ |
| 88 | #define DWMMC_INT_RCRC (1 << 6) /* Response CRC err */ |
| 89 | #define DWMMC_INT_RXDR (1 << 5) |
| 90 | #define DWMMC_INT_TXDR (1 << 4) |
| 91 | #define DWMMC_INT_DTO (1 << 3) /* Data trans over */ |
| 92 | #define DWMMC_INT_CMD_DONE (1 << 2) |
| 93 | #define DWMMC_INT_RE (1 << 1) |
| 94 | |
| 95 | #define DWMMC_IDMAC_DES0_DIC (1 << 1) |
| 96 | #define DWMMC_IDMAC_DES0_LD (1 << 2) |
| 97 | #define DWMMC_IDMAC_DES0_FS (1 << 3) |
| 98 | #define DWMMC_IDMAC_DES0_CH (1 << 4) |
| 99 | #define DWMMC_IDMAC_DES0_ER (1 << 5) |
| 100 | #define DWMMC_IDMAC_DES0_CES (1 << 30) |
| 101 | #define DWMMC_IDMAC_DES0_OWN (1 << 31) |
| 102 | #define DWMMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff) |
| 103 | #define DWMMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13) |
| 104 | #define DWMMC_IDMAC_SWRESET (1 << 0) |
| 105 | #define DWMMC_IDMAC_FB (1 << 1) |
| 106 | #define DWMMC_IDMAC_ENABLE (1 << 7) |
| 107 | |
| 108 | #define EMMC_FIX_RCA 6 |
| 109 | |
| 110 | /* bits in MMC0_CTRL */ |
| 111 | #define DWMMC_CTRL_RESET (1 << 0) |
| 112 | #define DWMMC_CTRL_FIFO_RESET (1 << 1) |
| 113 | #define DWMMC_CTRL_DMA_RESET (1 << 2) |
| 114 | #define DWMMC_CTRL_INT_EN (1 << 4) |
| 115 | #define DWMMC_CTRL_DMA_EN (1 << 5) |
| 116 | #define DWMMC_CTRL_IDMAC_EN (1 << 25) |
| 117 | #define DWMMC_CTRL_RESET_ALL (DWMMC_CTRL_RESET | DWMMC_CTRL_FIFO_RESET | DWMMC_CTRL_DMA_RESET) |
| 118 | |
| 119 | #define DWMMC_STS_DATA_BUSY (1 << 9) |
| 120 | |
| 121 | #define DWMMC_FIFO_TWMARK(x) (x & 0xfff) |
| 122 | #define DWMMC_FIFO_RWMARK(x) ((x & 0x1ff) << 16) |
| 123 | #define DWMMC_DMA_BURST_SIZE(x) ((x & 0x7) << 28) |
| 124 | |
| 125 | #define DWMMC_CARD_RD_THR(x) ((x & 0xfff) << 16) |
| 126 | #define DWMMC_CARD_RD_THR_EN (1 << 0) |
| 127 | |
| 128 | #endif // __DWMMC_H__ |