Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame^] | 1 | /** @file
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| 2 | Definition of the MMC Host Protocol
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| 3 |
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| 4 | Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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| 5 |
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| 6 | This program and the accompanying materials
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| 7 | are licensed and made available under the terms and conditions of the BSD License
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| 8 | which accompanies this distribution. The full text of the license may be found at
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| 9 | http://opensource.org/licenses/bsd-license.php
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| 10 |
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| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 13 |
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| 14 | **/
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| 15 |
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| 16 | #ifndef __MMC_HOST_H__
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| 17 | #define __MMC_HOST_H__
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| 18 |
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| 19 | ///
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| 20 | /// Global ID for the MMC Host Protocol
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| 21 | ///
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| 22 | #define EFI_MMC_HOST_PROTOCOL_GUID \
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| 23 | { 0x3e591c00, 0x9e4a, 0x11df, {0x92, 0x44, 0x00, 0x02, 0xA5, 0xD5, 0xC5, 0x1B } }
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| 24 |
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| 25 | #define MMC_RESPONSE_TYPE_R1 0
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| 26 | #define MMC_RESPONSE_TYPE_R1b 0
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| 27 | #define MMC_RESPONSE_TYPE_R2 1
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| 28 | #define MMC_RESPONSE_TYPE_R3 0
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| 29 | #define MMC_RESPONSE_TYPE_R6 0
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| 30 | #define MMC_RESPONSE_TYPE_R7 0
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| 31 | #define MMC_RESPONSE_TYPE_OCR 0
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| 32 | #define MMC_RESPONSE_TYPE_CID 1
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| 33 | #define MMC_RESPONSE_TYPE_CSD 1
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| 34 | #define MMC_RESPONSE_TYPE_RCA 0
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| 35 |
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| 36 | typedef UINT32 MMC_RESPONSE_TYPE;
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| 37 |
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| 38 | typedef UINT32 MMC_CMD;
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| 39 |
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| 40 | #define MMC_CMD_WAIT_RESPONSE (1 << 16)
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| 41 | #define MMC_CMD_LONG_RESPONSE (1 << 17)
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| 42 | #define MMC_CMD_NO_CRC_RESPONSE (1 << 18)
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| 43 |
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| 44 | #define MMC_INDX(Index) ((Index) & 0xFFFF)
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| 45 | #define MMC_GET_INDX(MmcCmd) ((MmcCmd) & 0xFFFF)
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| 46 |
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| 47 | #define MMC_CMD0 (MMC_INDX(0) | MMC_CMD_NO_CRC_RESPONSE)
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| 48 | #define MMC_CMD1 (MMC_INDX(1) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)
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| 49 | #define MMC_CMD2 (MMC_INDX(2) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE)
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| 50 | #define MMC_CMD3 (MMC_INDX(3) | MMC_CMD_WAIT_RESPONSE)
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| 51 | #define MMC_CMD5 (MMC_INDX(5) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)
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| 52 | #define MMC_CMD6 (MMC_INDX(6) | MMC_CMD_WAIT_RESPONSE)
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| 53 | #define MMC_CMD7 (MMC_INDX(7) | MMC_CMD_WAIT_RESPONSE)
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| 54 | #define MMC_CMD8 (MMC_INDX(8) | MMC_CMD_WAIT_RESPONSE)
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| 55 | #define MMC_CMD9 (MMC_INDX(9) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE)
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| 56 | #define MMC_CMD11 (MMC_INDX(11) | MMC_CMD_WAIT_RESPONSE)
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| 57 | #define MMC_CMD12 (MMC_INDX(12) | MMC_CMD_WAIT_RESPONSE)
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| 58 | #define MMC_CMD13 (MMC_INDX(13) | MMC_CMD_WAIT_RESPONSE)
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| 59 | #define MMC_CMD16 (MMC_INDX(16) | MMC_CMD_WAIT_RESPONSE)
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| 60 | #define MMC_CMD17 (MMC_INDX(17) | MMC_CMD_WAIT_RESPONSE)
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| 61 | #define MMC_CMD18 (MMC_INDX(18) | MMC_CMD_WAIT_RESPONSE)
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| 62 | #define MMC_CMD20 (MMC_INDX(20) | MMC_CMD_WAIT_RESPONSE)
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| 63 | #define MMC_CMD23 (MMC_INDX(23) | MMC_CMD_WAIT_RESPONSE)
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| 64 | #define MMC_CMD24 (MMC_INDX(24) | MMC_CMD_WAIT_RESPONSE)
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| 65 | #define MMC_CMD25 (MMC_INDX(25) | MMC_CMD_WAIT_RESPONSE)
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| 66 | #define MMC_CMD51 (MMC_INDX(51) | MMC_CMD_WAIT_RESPONSE)
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| 67 | #define MMC_CMD55 (MMC_INDX(55) | MMC_CMD_WAIT_RESPONSE)
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| 68 | #define MMC_ACMD41 (MMC_INDX(41) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)
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| 69 |
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| 70 | // Valid responses for CMD1 in eMMC
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| 71 | #define EMMC_CMD1_CAPACITY_LESS_THAN_2GB 0x00FF8080 // Capacity <= 2GB, byte addressing used
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| 72 | #define EMMC_CMD1_CAPACITY_GREATER_THAN_2GB 0x40FF8080 // Capacity > 2GB, 512-byte sector addressing used
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| 73 |
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| 74 | typedef enum _MMC_STATE {
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| 75 | MmcInvalidState = 0,
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| 76 | MmcHwInitializationState,
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| 77 | MmcIdleState,
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| 78 | MmcReadyState,
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| 79 | MmcIdentificationState,
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| 80 | MmcStandByState,
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| 81 | MmcTransferState,
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| 82 | MmcSendingDataState,
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| 83 | MmcReceiveDataState,
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| 84 | MmcProgrammingState,
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| 85 | MmcDisconnectState,
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| 86 | } MMC_STATE;
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| 87 |
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| 88 | #define EMMCBACKWARD (0)
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| 89 | #define EMMCHS26 (1 << 0) // High-Speed @26MHz at rated device voltages
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| 90 | #define EMMCHS52 (1 << 1) // High-Speed @52MHz at rated device voltages
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| 91 | #define EMMCHS52DDR1V8 (1 << 2) // High-Speed Dual Data Rate @52MHz 1.8V or 3V I/O
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| 92 | #define EMMCHS52DDR1V2 (1 << 3) // High-Speed Dual Data Rate @52MHz 1.2V I/O
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| 93 | #define EMMCHS200SDR1V8 (1 << 4) // HS200 Single Data Rate @200MHz 1.8V I/O
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| 94 | #define EMMCHS200SDR1V2 (1 << 5) // HS200 Single Data Rate @200MHz 1.2V I/O
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| 95 | #define EMMCHS400DDR1V8 (1 << 6) // HS400 Dual Data Rate @400MHz 1.8V I/O
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| 96 | #define EMMCHS400DDR1V2 (1 << 7) // HS400 Dual Data Rate @400MHz 1.2V I/O
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| 97 |
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| 98 | ///
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| 99 | /// Forward declaration for EFI_MMC_HOST_PROTOCOL
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| 100 | ///
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| 101 | typedef struct _EFI_MMC_HOST_PROTOCOL EFI_MMC_HOST_PROTOCOL;
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| 102 |
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| 103 | typedef BOOLEAN (EFIAPI *MMC_ISCARDPRESENT) (
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| 104 | IN EFI_MMC_HOST_PROTOCOL *This
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| 105 | );
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| 106 |
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| 107 | typedef BOOLEAN (EFIAPI *MMC_ISREADONLY) (
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| 108 | IN EFI_MMC_HOST_PROTOCOL *This
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| 109 | );
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| 110 |
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| 111 | typedef BOOLEAN (EFIAPI *MMC_ISDMASUPPORTED) (
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| 112 | IN EFI_MMC_HOST_PROTOCOL *This
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| 113 | );
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| 114 |
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| 115 | typedef EFI_STATUS (EFIAPI *MMC_BUILDDEVICEPATH) (
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| 116 | IN EFI_MMC_HOST_PROTOCOL *This,
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| 117 | OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
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| 118 | );
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| 119 |
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| 120 | typedef EFI_STATUS (EFIAPI *MMC_NOTIFYSTATE) (
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| 121 | IN EFI_MMC_HOST_PROTOCOL *This,
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| 122 | IN MMC_STATE State
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| 123 | );
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| 124 |
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| 125 | typedef EFI_STATUS (EFIAPI *MMC_SENDCOMMAND) (
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| 126 | IN EFI_MMC_HOST_PROTOCOL *This,
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| 127 | IN MMC_CMD Cmd,
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| 128 | IN UINT32 Argument
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| 129 | );
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| 130 |
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| 131 | typedef EFI_STATUS (EFIAPI *MMC_RECEIVERESPONSE) (
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| 132 | IN EFI_MMC_HOST_PROTOCOL *This,
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| 133 | IN MMC_RESPONSE_TYPE Type,
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| 134 | IN UINT32 *Buffer
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| 135 | );
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| 136 |
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| 137 | typedef EFI_STATUS (EFIAPI *MMC_READBLOCKDATA) (
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| 138 | IN EFI_MMC_HOST_PROTOCOL *This,
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| 139 | IN EFI_LBA Lba,
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| 140 | IN UINTN Length,
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| 141 | OUT UINT32 *Buffer
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| 142 | );
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| 143 |
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| 144 | typedef EFI_STATUS (EFIAPI *MMC_WRITEBLOCKDATA) (
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| 145 | IN EFI_MMC_HOST_PROTOCOL *This,
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| 146 | IN EFI_LBA Lba,
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| 147 | IN UINTN Length,
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| 148 | IN UINT32 *Buffer
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| 149 | );
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| 150 |
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| 151 | typedef EFI_STATUS (EFIAPI *MMC_SETIOS) (
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| 152 | IN EFI_MMC_HOST_PROTOCOL *This,
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| 153 | IN UINT32 BusClockFreq,
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| 154 | IN UINT32 BusWidth,
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| 155 | IN UINT32 TimingMode
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| 156 | );
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| 157 |
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| 158 |
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| 159 | struct _EFI_MMC_HOST_PROTOCOL {
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| 160 |
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| 161 | UINT32 Revision;
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| 162 | MMC_ISCARDPRESENT IsCardPresent;
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| 163 | MMC_ISREADONLY IsReadOnly;
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| 164 | MMC_ISDMASUPPORTED IsDmaSupported;
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| 165 | MMC_BUILDDEVICEPATH BuildDevicePath;
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| 166 |
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| 167 | MMC_NOTIFYSTATE NotifyState;
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| 168 |
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| 169 | MMC_SENDCOMMAND SendCommand;
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| 170 | MMC_RECEIVERESPONSE ReceiveResponse;
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| 171 |
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| 172 | MMC_READBLOCKDATA ReadBlockData;
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| 173 | MMC_WRITEBLOCKDATA WriteBlockData;
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| 174 |
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| 175 | MMC_SETIOS SetIos;
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| 176 |
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| 177 | };
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| 178 |
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| 179 | #define MMC_HOST_PROTOCOL_REVISION 0x00010001 // 1.1
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| 180 |
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| 181 | extern EFI_GUID gEfiMmcHostProtocolGuid;
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| 182 |
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| 183 | #endif
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| 184 |
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