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Vishal Bhoj82c80712015-12-15 21:13:33 +05301/** @file
2 Definition of the MMC Host Protocol
3
4 Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14**/
15
16#ifndef __MMC_HOST_H__
17#define __MMC_HOST_H__
18
19///
20/// Global ID for the MMC Host Protocol
21///
22#define EFI_MMC_HOST_PROTOCOL_GUID \
23 { 0x3e591c00, 0x9e4a, 0x11df, {0x92, 0x44, 0x00, 0x02, 0xA5, 0xD5, 0xC5, 0x1B } }
24
25#define MMC_RESPONSE_TYPE_R1 0
26#define MMC_RESPONSE_TYPE_R1b 0
27#define MMC_RESPONSE_TYPE_R2 1
28#define MMC_RESPONSE_TYPE_R3 0
29#define MMC_RESPONSE_TYPE_R6 0
30#define MMC_RESPONSE_TYPE_R7 0
31#define MMC_RESPONSE_TYPE_OCR 0
32#define MMC_RESPONSE_TYPE_CID 1
33#define MMC_RESPONSE_TYPE_CSD 1
34#define MMC_RESPONSE_TYPE_RCA 0
35
36typedef UINT32 MMC_RESPONSE_TYPE;
37
38typedef UINT32 MMC_CMD;
39
40#define MMC_CMD_WAIT_RESPONSE (1 << 16)
41#define MMC_CMD_LONG_RESPONSE (1 << 17)
42#define MMC_CMD_NO_CRC_RESPONSE (1 << 18)
43
44#define MMC_INDX(Index) ((Index) & 0xFFFF)
45#define MMC_GET_INDX(MmcCmd) ((MmcCmd) & 0xFFFF)
46
47#define MMC_CMD0 (MMC_INDX(0) | MMC_CMD_NO_CRC_RESPONSE)
48#define MMC_CMD1 (MMC_INDX(1) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)
49#define MMC_CMD2 (MMC_INDX(2) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE)
50#define MMC_CMD3 (MMC_INDX(3) | MMC_CMD_WAIT_RESPONSE)
51#define MMC_CMD5 (MMC_INDX(5) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)
52#define MMC_CMD6 (MMC_INDX(6) | MMC_CMD_WAIT_RESPONSE)
53#define MMC_CMD7 (MMC_INDX(7) | MMC_CMD_WAIT_RESPONSE)
54#define MMC_CMD8 (MMC_INDX(8) | MMC_CMD_WAIT_RESPONSE)
55#define MMC_CMD9 (MMC_INDX(9) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_LONG_RESPONSE)
56#define MMC_CMD11 (MMC_INDX(11) | MMC_CMD_WAIT_RESPONSE)
57#define MMC_CMD12 (MMC_INDX(12) | MMC_CMD_WAIT_RESPONSE)
58#define MMC_CMD13 (MMC_INDX(13) | MMC_CMD_WAIT_RESPONSE)
59#define MMC_CMD16 (MMC_INDX(16) | MMC_CMD_WAIT_RESPONSE)
60#define MMC_CMD17 (MMC_INDX(17) | MMC_CMD_WAIT_RESPONSE)
61#define MMC_CMD18 (MMC_INDX(18) | MMC_CMD_WAIT_RESPONSE)
62#define MMC_CMD20 (MMC_INDX(20) | MMC_CMD_WAIT_RESPONSE)
63#define MMC_CMD23 (MMC_INDX(23) | MMC_CMD_WAIT_RESPONSE)
64#define MMC_CMD24 (MMC_INDX(24) | MMC_CMD_WAIT_RESPONSE)
65#define MMC_CMD25 (MMC_INDX(25) | MMC_CMD_WAIT_RESPONSE)
66#define MMC_CMD51 (MMC_INDX(51) | MMC_CMD_WAIT_RESPONSE)
67#define MMC_CMD55 (MMC_INDX(55) | MMC_CMD_WAIT_RESPONSE)
68#define MMC_ACMD41 (MMC_INDX(41) | MMC_CMD_WAIT_RESPONSE | MMC_CMD_NO_CRC_RESPONSE)
69
70// Valid responses for CMD1 in eMMC
71#define EMMC_CMD1_CAPACITY_LESS_THAN_2GB 0x00FF8080 // Capacity <= 2GB, byte addressing used
72#define EMMC_CMD1_CAPACITY_GREATER_THAN_2GB 0x40FF8080 // Capacity > 2GB, 512-byte sector addressing used
73
74typedef enum _MMC_STATE {
75 MmcInvalidState = 0,
76 MmcHwInitializationState,
77 MmcIdleState,
78 MmcReadyState,
79 MmcIdentificationState,
80 MmcStandByState,
81 MmcTransferState,
82 MmcSendingDataState,
83 MmcReceiveDataState,
84 MmcProgrammingState,
85 MmcDisconnectState,
86} MMC_STATE;
87
88#define EMMCBACKWARD (0)
89#define EMMCHS26 (1 << 0) // High-Speed @26MHz at rated device voltages
90#define EMMCHS52 (1 << 1) // High-Speed @52MHz at rated device voltages
91#define EMMCHS52DDR1V8 (1 << 2) // High-Speed Dual Data Rate @52MHz 1.8V or 3V I/O
92#define EMMCHS52DDR1V2 (1 << 3) // High-Speed Dual Data Rate @52MHz 1.2V I/O
93#define EMMCHS200SDR1V8 (1 << 4) // HS200 Single Data Rate @200MHz 1.8V I/O
94#define EMMCHS200SDR1V2 (1 << 5) // HS200 Single Data Rate @200MHz 1.2V I/O
95#define EMMCHS400DDR1V8 (1 << 6) // HS400 Dual Data Rate @400MHz 1.8V I/O
96#define EMMCHS400DDR1V2 (1 << 7) // HS400 Dual Data Rate @400MHz 1.2V I/O
97
98///
99/// Forward declaration for EFI_MMC_HOST_PROTOCOL
100///
101typedef struct _EFI_MMC_HOST_PROTOCOL EFI_MMC_HOST_PROTOCOL;
102
103typedef BOOLEAN (EFIAPI *MMC_ISCARDPRESENT) (
104 IN EFI_MMC_HOST_PROTOCOL *This
105 );
106
107typedef BOOLEAN (EFIAPI *MMC_ISREADONLY) (
108 IN EFI_MMC_HOST_PROTOCOL *This
109 );
110
111typedef BOOLEAN (EFIAPI *MMC_ISDMASUPPORTED) (
112 IN EFI_MMC_HOST_PROTOCOL *This
113 );
114
115typedef EFI_STATUS (EFIAPI *MMC_BUILDDEVICEPATH) (
116 IN EFI_MMC_HOST_PROTOCOL *This,
117 OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
118 );
119
120typedef EFI_STATUS (EFIAPI *MMC_NOTIFYSTATE) (
121 IN EFI_MMC_HOST_PROTOCOL *This,
122 IN MMC_STATE State
123 );
124
125typedef EFI_STATUS (EFIAPI *MMC_SENDCOMMAND) (
126 IN EFI_MMC_HOST_PROTOCOL *This,
127 IN MMC_CMD Cmd,
128 IN UINT32 Argument
129 );
130
131typedef EFI_STATUS (EFIAPI *MMC_RECEIVERESPONSE) (
132 IN EFI_MMC_HOST_PROTOCOL *This,
133 IN MMC_RESPONSE_TYPE Type,
134 IN UINT32 *Buffer
135 );
136
137typedef EFI_STATUS (EFIAPI *MMC_READBLOCKDATA) (
138 IN EFI_MMC_HOST_PROTOCOL *This,
139 IN EFI_LBA Lba,
140 IN UINTN Length,
141 OUT UINT32 *Buffer
142 );
143
144typedef EFI_STATUS (EFIAPI *MMC_WRITEBLOCKDATA) (
145 IN EFI_MMC_HOST_PROTOCOL *This,
146 IN EFI_LBA Lba,
147 IN UINTN Length,
148 IN UINT32 *Buffer
149 );
150
151typedef EFI_STATUS (EFIAPI *MMC_SETIOS) (
152 IN EFI_MMC_HOST_PROTOCOL *This,
153 IN UINT32 BusClockFreq,
154 IN UINT32 BusWidth,
155 IN UINT32 TimingMode
156 );
157
158
159struct _EFI_MMC_HOST_PROTOCOL {
160
161 UINT32 Revision;
162 MMC_ISCARDPRESENT IsCardPresent;
163 MMC_ISREADONLY IsReadOnly;
164 MMC_ISDMASUPPORTED IsDmaSupported;
165 MMC_BUILDDEVICEPATH BuildDevicePath;
166
167 MMC_NOTIFYSTATE NotifyState;
168
169 MMC_SENDCOMMAND SendCommand;
170 MMC_RECEIVERESPONSE ReceiveResponse;
171
172 MMC_READBLOCKDATA ReadBlockData;
173 MMC_WRITEBLOCKDATA WriteBlockData;
174
175 MMC_SETIOS SetIos;
176
177};
178
179#define MMC_HOST_PROTOCOL_REVISION 0x00010001 // 1.1
180
181extern EFI_GUID gEfiMmcHostProtocolGuid;
182
183#endif
184