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gerrit.devboardsforandroid.linaro.org / device / linaro / hikey960 / 82c807137a2c3f033e23e414476d131e88ad221a / . / uefi / linaro-edk2 / MdePkg / Include / Protocol / PciIo.h
blob: 6068260be69ddbf592cee47571b5d8fa71f8c661 [file] [log] [blame]
Vishal Bhoj82c80712015-12-15 21:13:33 +0530[diff] [blame^]1/** @file
2 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,
3 and DMA interfaces that a driver uses to access its PCI controller.
4
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14**/
15
16#ifndef __PCI_IO_H__
17#define __PCI_IO_H__
18
19///
20/// Global ID for the PCI I/O Protocol
21///
22#define EFI_PCI_IO_PROTOCOL_GUID \
23 { \
24 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \
25 }
26
27typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;
28
29///
30/// *******************************************************
31/// EFI_PCI_IO_PROTOCOL_WIDTH
32/// *******************************************************
33///
34typedef enum {
35 EfiPciIoWidthUint8 = 0,
36 EfiPciIoWidthUint16,
37 EfiPciIoWidthUint32,
38 EfiPciIoWidthUint64,
39 EfiPciIoWidthFifoUint8,
40 EfiPciIoWidthFifoUint16,
41 EfiPciIoWidthFifoUint32,
42 EfiPciIoWidthFifoUint64,
43 EfiPciIoWidthFillUint8,
44 EfiPciIoWidthFillUint16,
45 EfiPciIoWidthFillUint32,
46 EfiPciIoWidthFillUint64,
47 EfiPciIoWidthMaximum
48} EFI_PCI_IO_PROTOCOL_WIDTH;
49
50//
51// Complete PCI address generater
52//
53#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged
54#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles
55#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)
56#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)
57#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)
58#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)
59#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)
60#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)
61#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)
62#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined
63#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header
64#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header
65#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header
66#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached
67#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range
68#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
69#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR
70#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC
71#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)
72#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)
73#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)
74
75#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)
76#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)
77
78///
79/// *******************************************************
80/// EFI_PCI_IO_PROTOCOL_OPERATION
81/// *******************************************************
82///
83typedef enum {
84 ///
85 /// A read operation from system memory by a bus master.
86 ///
87 EfiPciIoOperationBusMasterRead,
88 ///
89 /// A write operation from system memory by a bus master.
90 ///
91 EfiPciIoOperationBusMasterWrite,
92 ///
93 /// Provides both read and write access to system memory by both the processor and a
94 /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.
95 ///
96 EfiPciIoOperationBusMasterCommonBuffer,
97 EfiPciIoOperationMaximum
98} EFI_PCI_IO_PROTOCOL_OPERATION;
99
100///
101/// *******************************************************
102/// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION
103/// *******************************************************
104///
105typedef enum {
106 ///
107 /// Retrieve the PCI controller's current attributes, and return them in Result.
108 ///
109 EfiPciIoAttributeOperationGet,
110 ///
111 /// Set the PCI controller's current attributes to Attributes.
112 ///
113 EfiPciIoAttributeOperationSet,
114 ///
115 /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.
116 ///
117 EfiPciIoAttributeOperationEnable,
118 ///
119 /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller.
120 ///
121 EfiPciIoAttributeOperationDisable,
122 ///
123 /// Retrieve the PCI controller's supported attributes, and return them in Result.
124 ///
125 EfiPciIoAttributeOperationSupported,
126 EfiPciIoAttributeOperationMaximum
127} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;
128
129/**
130 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
131 satisfied or after a defined duration.
132
133 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
134 @param Width Signifies the width of the memory or I/O operations.
135 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
136 base address for the memory operation to perform.
137 @param Offset The offset within the selected BAR to start the memory operation.
138 @param Mask Mask used for the polling criteria.
139 @param Value The comparison value used for the polling exit criteria.
140 @param Delay The number of 100 ns units to poll.
141 @param Result Pointer to the last value read from the memory location.
142
143 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
144 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
145 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
146 @retval EFI_TIMEOUT Delay expired before a match occurred.
147 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
148 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
149
150**/
151typedef
152EFI_STATUS
153(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)(
154 IN EFI_PCI_IO_PROTOCOL *This,
155 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
156 IN UINT8 BarIndex,
157 IN UINT64 Offset,
158 IN UINT64 Mask,
159 IN UINT64 Value,
160 IN UINT64 Delay,
161 OUT UINT64 *Result
162 );
163
164/**
165 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
166
167 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
168 @param Width Signifies the width of the memory or I/O operations.
169 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
170 base address for the memory or I/O operation to perform.
171 @param Offset The offset within the selected BAR to start the memory or I/O operation.
172 @param Count The number of memory or I/O operations to perform.
173 @param Buffer For read operations, the destination buffer to store the results. For write
174 operations, the source buffer to write data from.
175
176 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
177 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
178 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
179 valid for the PCI BAR specified by BarIndex.
180 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
181 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
182
183**/
184typedef
185EFI_STATUS
186(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)(
187 IN EFI_PCI_IO_PROTOCOL *This,
188 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
189 IN UINT8 BarIndex,
190 IN UINT64 Offset,
191 IN UINTN Count,
192 IN OUT VOID *Buffer
193 );
194
195typedef struct {
196 ///
197 /// Read PCI controller registers in the PCI memory or I/O space.
198 ///
199 EFI_PCI_IO_PROTOCOL_IO_MEM Read;
200 ///
201 /// Write PCI controller registers in the PCI memory or I/O space.
202 ///
203 EFI_PCI_IO_PROTOCOL_IO_MEM Write;
204} EFI_PCI_IO_PROTOCOL_ACCESS;
205
206/**
207 Enable a PCI driver to access PCI controller registers in PCI configuration space.
208
209 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
210 @param Width Signifies the width of the memory operations.
211 @param Offset The offset within the PCI configuration space for the PCI controller.
212 @param Count The number of PCI configuration operations to perform.
213 @param Buffer For read operations, the destination buffer to store the results. For write
214 operations, the source buffer to write data from.
215
216
217 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
218 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
219 valid for the PCI configuration header of the PCI controller.
220 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
221 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
222
223**/
224typedef
225EFI_STATUS
226(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)(
227 IN EFI_PCI_IO_PROTOCOL *This,
228 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
229 IN UINT32 Offset,
230 IN UINTN Count,
231 IN OUT VOID *Buffer
232 );
233
234typedef struct {
235 ///
236 /// Read PCI controller registers in PCI configuration space.
237 ///
238 EFI_PCI_IO_PROTOCOL_CONFIG Read;
239 ///
240 /// Write PCI controller registers in PCI configuration space.
241 ///
242 EFI_PCI_IO_PROTOCOL_CONFIG Write;
243} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;
244
245/**
246 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
247 memory space.
248
249 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
250 @param Width Signifies the width of the memory operations.
251 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the
252 base address for the memory operation to perform.
253 @param DestOffset The destination offset within the BAR specified by DestBarIndex to
254 start the memory writes for the copy operation.
255 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the
256 base address for the memory operation to perform.
257 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start
258 the memory reads for the copy operation.
259 @param Count The number of memory operations to perform. Bytes moved is Width
260 size * Count, starting at DestOffset and SrcOffset.
261
262 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
263 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
264 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
265 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count
266 is not valid for the PCI BAR specified by DestBarIndex.
267 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is
268 not valid for the PCI BAR specified by SrcBarIndex.
269 @retval EFI_INVALID_PARAMETER Width is invalid.
270 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
271
272**/
273typedef
274EFI_STATUS
275(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)(
276 IN EFI_PCI_IO_PROTOCOL *This,
277 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
278 IN UINT8 DestBarIndex,
279 IN UINT64 DestOffset,
280 IN UINT8 SrcBarIndex,
281 IN UINT64 SrcOffset,
282 IN UINTN Count
283 );
284
285/**
286 Provides the PCI controller-specific addresses needed to access system memory.
287
288 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
289 @param Operation Indicates if the bus master is going to read or write to system memory.
290 @param HostAddress The system memory address to map to the PCI controller.
291 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
292 that were mapped.
293 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
294 access the hosts HostAddress.
295 @param Mapping A resulting value to pass to Unmap().
296
297 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
298 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
299 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
300 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
301 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
302
303**/
304typedef
305EFI_STATUS
306(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)(
307 IN EFI_PCI_IO_PROTOCOL *This,
308 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
309 IN VOID *HostAddress,
310 IN OUT UINTN *NumberOfBytes,
311 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
312 OUT VOID **Mapping
313 );
314
315/**
316 Completes the Map() operation and releases any corresponding resources.
317
318 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
319 @param Mapping The mapping value returned from Map().
320
321 @retval EFI_SUCCESS The range was unmapped.
322 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
323
324**/
325typedef
326EFI_STATUS
327(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)(
328 IN EFI_PCI_IO_PROTOCOL *This,
329 IN VOID *Mapping
330 );
331
332/**
333 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
334 mapping.
335
336 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
337 @param Type This parameter is not used and must be ignored.
338 @param MemoryType The type of memory to allocate, EfiBootServicesData or
339 EfiRuntimeServicesData.
340 @param Pages The number of pages to allocate.
341 @param HostAddress A pointer to store the base system memory address of the
342 allocated range.
343 @param Attributes The requested bit mask of attributes for the allocated range.
344
345 @retval EFI_SUCCESS The requested memory pages were allocated.
346 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
347 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
348 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
349 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
350
351**/
352typedef
353EFI_STATUS
354(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)(
355 IN EFI_PCI_IO_PROTOCOL *This,
356 IN EFI_ALLOCATE_TYPE Type,
357 IN EFI_MEMORY_TYPE MemoryType,
358 IN UINTN Pages,
359 OUT VOID **HostAddress,
360 IN UINT64 Attributes
361 );
362
363/**
364 Frees memory that was allocated with AllocateBuffer().
365
366 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
367 @param Pages The number of pages to free.
368 @param HostAddress The base system memory address of the allocated range.
369
370 @retval EFI_SUCCESS The requested memory pages were freed.
371 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
372 was not allocated with AllocateBuffer().
373
374**/
375typedef
376EFI_STATUS
377(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)(
378 IN EFI_PCI_IO_PROTOCOL *This,
379 IN UINTN Pages,
380 IN VOID *HostAddress
381 );
382
383/**
384 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
385
386 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
387
388 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
389 bridge to system memory.
390 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
391 host bridge due to a hardware error.
392
393**/
394typedef
395EFI_STATUS
396(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)(
397 IN EFI_PCI_IO_PROTOCOL *This
398 );
399
400/**
401 Retrieves this PCI controller's current PCI bus number, device number, and function number.
402
403 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
404 @param SegmentNumber The PCI controller's current PCI segment number.
405 @param BusNumber The PCI controller's current PCI bus number.
406 @param DeviceNumber The PCI controller's current PCI device number.
407 @param FunctionNumber The PCI controller's current PCI function number.
408
409 @retval EFI_SUCCESS The PCI controller location was returned.
410 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
411
412**/
413typedef
414EFI_STATUS
415(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)(
416 IN EFI_PCI_IO_PROTOCOL *This,
417 OUT UINTN *SegmentNumber,
418 OUT UINTN *BusNumber,
419 OUT UINTN *DeviceNumber,
420 OUT UINTN *FunctionNumber
421 );
422
423/**
424 Performs an operation on the attributes that this PCI controller supports. The operations include
425 getting the set of supported attributes, retrieving the current attributes, setting the current
426 attributes, enabling attributes, and disabling attributes.
427
428 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
429 @param Operation The operation to perform on the attributes for this PCI controller.
430 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
431 operations.
432 @param Result A pointer to the result mask of attributes that are returned for the Get
433 and Supported operations.
434
435 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
436 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
437 @retval EFI_UNSUPPORTED one or more of the bits set in
438 Attributes are not supported by this PCI controller or one of
439 its parent bridges when Operation is Set, Enable or Disable.
440
441**/
442typedef
443EFI_STATUS
444(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)(
445 IN EFI_PCI_IO_PROTOCOL *This,
446 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
447 IN UINT64 Attributes,
448 OUT UINT64 *Result OPTIONAL
449 );
450
451/**
452 Gets the attributes that this PCI controller supports setting on a BAR using
453 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
454
455 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
456 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
457 base address for resource range. The legal range for this field is 0..5.
458 @param Supports A pointer to the mask of attributes that this PCI controller supports
459 setting for this BAR with SetBarAttributes().
460 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current
461 configuration of this BAR of the PCI controller.
462
463 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI
464 controller supports are returned in Supports. If Resources
465 is not NULL, then the ACPI 2.0 resource descriptors that the PCI
466 controller is currently using are returned in Resources.
467 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
468 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
469 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate
470 Resources.
471
472**/
473typedef
474EFI_STATUS
475(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)(
476 IN EFI_PCI_IO_PROTOCOL *This,
477 IN UINT8 BarIndex,
478 OUT UINT64 *Supports, OPTIONAL
479 OUT VOID **Resources OPTIONAL
480 );
481
482/**
483 Sets the attributes for a range of a BAR on a PCI controller.
484
485 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
486 @param Attributes The mask of attributes to set for the resource range specified by
487 BarIndex, Offset, and Length.
488 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
489 base address for resource range. The legal range for this field is 0..5.
490 @param Offset A pointer to the BAR relative base address of the resource range to be
491 modified by the attributes specified by Attributes.
492 @param Length A pointer to the length of the resource range to be modified by the
493 attributes specified by Attributes.
494
495 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource
496 range specified by BarIndex, Offset, and Length were
497 set on the PCI controller, and the actual resource range is returned
498 in Offset and Length.
499 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
500 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
501 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the
502 resource range specified by BarIndex, Offset, and
503 Length.
504
505**/
506typedef
507EFI_STATUS
508(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)(
509 IN EFI_PCI_IO_PROTOCOL *This,
510 IN UINT64 Attributes,
511 IN UINT8 BarIndex,
512 IN OUT UINT64 *Offset,
513 IN OUT UINT64 *Length
514 );
515
516///
517/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration,
518/// and DMA interfaces used to abstract accesses to PCI controllers.
519/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.
520/// A device driver that wishes to manage a PCI controller in a system will have to
521/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.
522///
523struct _EFI_PCI_IO_PROTOCOL {
524 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;
525 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;
526 EFI_PCI_IO_PROTOCOL_ACCESS Mem;
527 EFI_PCI_IO_PROTOCOL_ACCESS Io;
528 EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;
529 EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;
530 EFI_PCI_IO_PROTOCOL_MAP Map;
531 EFI_PCI_IO_PROTOCOL_UNMAP Unmap;
532 EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;
533 EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;
534 EFI_PCI_IO_PROTOCOL_FLUSH Flush;
535 EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;
536 EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;
537 EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;
538 EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;
539
540 ///
541 /// The size, in bytes, of the ROM image.
542 ///
543 UINT64 RomSize;
544
545 ///
546 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
547 /// for allocating memory for the ROM image, and copying the contents of the ROM to memory.
548 /// The contents of this buffer are either from the PCI option ROM that can be accessed
549 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.
550 /// The Attributes() function can be used to determine from which of these two sources
551 /// the RomImage buffer was initialized.
552 ///
553 VOID *RomImage;
554};
555
556extern EFI_GUID gEfiPciIoProtocolGuid;
557
558#endif