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gerrit.devboardsforandroid.linaro.org / device / linaro / hikey960 / 82c807137a2c3f033e23e414476d131e88ad221a / . / uefi / linaro-edk2 / OvmfPkg / AcpiTables / Dsdt.asl
blob: 519a31250a45a18f6309a0b62c15b8e97923d2e9 [file] [log] [blame]
Vishal Bhoj82c80712015-12-15 21:13:33 +0530[diff] [blame^]1/** @file
2 Contains root level name space objects for the platform
3
4 Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 4) {
16 //
17 // System Sleep States
18 //
19 // We build S3 and S4 with GetSuspendStates() in
20 // "OvmfPkg/AcpiPlatformDxe/Qemu.c".
21 //
22 Name (\_S0, Package () {5, 0, 0, 0}) // Working
23 Name (\_S5, Package () {0, 0, 0, 0}) // Soft Off
24
25 //
26 // System Bus
27 //
28 Scope (\_SB) {
29 //
30 // PCI Root Bridge
31 //
32 Device (PCI0) {
33 Name (_HID, EISAID ("PNP0A03"))
34 Name (_ADR, 0x00000000)
35 Name (_BBN, 0x00)
36 Name (_UID, 0x00)
37
38 //
39 // BUS, I/O, and MMIO resources
40 //
41 Name (CRES, ResourceTemplate () {
42 WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
43 ResourceProducer, // bit 0 of general flags is 1
44 MinFixed, // Range is fixed
45 MaxFixed, // Range is fixed
46 PosDecode, // PosDecode
47 0x0000, // Granularity
48 0x0000, // Min
49 0x00FF, // Max
50 0x0000, // Translation
51 0x0100 // Range Length = Max-Min+1
52 )
53
54 IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF)
55
56 WORDIO ( // Consumed-and-produced resource (all I/O below CF8)
57 ResourceProducer, // bit 0 of general flags is 0
58 MinFixed, // Range is fixed
59 MaxFixed, // Range is fixed
60 PosDecode,
61 EntireRange,
62 0x0000, // Granularity
63 0x0000, // Min
64 0x0CF7, // Max
65 0x0000, // Translation
66 0x0CF8 // Range Length
67 )
68
69 WORDIO ( // Consumed-and-produced resource (all I/O above CFF)
70 ResourceProducer, // bit 0 of general flags is 0
71 MinFixed, // Range is fixed
72 MaxFixed, // Range is fixed
73 PosDecode,
74 EntireRange,
75 0x0000, // Granularity
76 0x0D00, // Min
77 0xFFFF, // Max
78 0x0000, // Translation
79 0xF300 // Range Length
80 )
81
82 DWORDMEMORY ( // Descriptor for legacy VGA video RAM
83 ResourceProducer, // bit 0 of general flags is 0
84 PosDecode,
85 MinFixed, // Range is fixed
86 MaxFixed, // Range is Fixed
87 Cacheable,
88 ReadWrite,
89 0x00000000, // Granularity
90 0x000A0000, // Min
91 0x000BFFFF, // Max
92 0x00000000, // Translation
93 0x00020000 // Range Length
94 )
95
96 DWORDMEMORY ( // Descriptor for 32-bit MMIO
97 ResourceProducer, // bit 0 of general flags is 0
98 PosDecode,
99 MinFixed, // Range is fixed
100 MaxFixed, // Range is Fixed
101 NonCacheable,
102 ReadWrite,
103 0x00000000, // Granularity
104 0xF8000000, // Min
105 0xFFFBFFFF, // Max
106 0x00000000, // Translation
107 0x07FC0000, // Range Length
108 , // ResourceSourceIndex
109 , // ResourceSource
110 PW32 // DescriptorName
111 )
112 })
113
114 Name (CR64, ResourceTemplate () {
115 QWordMemory ( // Descriptor for 64-bit MMIO
116 ResourceProducer, // bit 0 of general flags is 0
117 PosDecode,
118 MinFixed, // Range is fixed
119 MaxFixed, // Range is Fixed
120 Cacheable,
121 ReadWrite,
122 0x00000000, // Granularity
123 0x8000000000, // Min
124 0xFFFFFFFFFF, // Max
125 0x00000000, // Translation
126 0x8000000000, // Range Length
127 , // ResourceSourceIndex
128 , // ResourceSource
129 PW64 // DescriptorName
130 )
131 })
132
133 Method (_CRS, 0) {
134 //
135 // see the FIRMWARE_DATA structure in "OvmfPkg/AcpiPlatformDxe/Qemu.c"
136 //
137 External (FWDT, OpRegionObj)
138 Field(FWDT, QWordAcc, NoLock, Preserve) {
139 P0S, 64, // PciWindow32.Base
140 P0E, 64, // PciWindow32.End
141 P0L, 64, // PciWindow32.Length
142 P1S, 64, // PciWindow64.Base
143 P1E, 64, // PciWindow64.End
144 P1L, 64 // PciWindow64.Length
145 }
146 Field(FWDT, DWordAcc, NoLock, Preserve) {
147 P0SL, 32, // PciWindow32.Base, low 32 bits
148 P0SH, 32, // PciWindow32.Base, high 32 bits
149 P0EL, 32, // PciWindow32.End, low 32 bits
150 P0EH, 32, // PciWindow32.End, high 32 bits
151 P0LL, 32, // PciWindow32.Length, low 32 bits
152 P0LH, 32, // PciWindow32.Length, high 32 bits
153 P1SL, 32, // PciWindow64.Base, low 32 bits
154 P1SH, 32, // PciWindow64.Base, high 32 bits
155 P1EL, 32, // PciWindow64.End, low 32 bits
156 P1EH, 32, // PciWindow64.End, high 32 bits
157 P1LL, 32, // PciWindow64.Length, low 32 bits
158 P1LH, 32 // PciWindow64.Length, high 32 bits
159 }
160
161 //
162 // fixup 32-bit PCI IO window
163 //
164 CreateDWordField (CRES, \_SB.PCI0.PW32._MIN, PS32)
165 CreateDWordField (CRES, \_SB.PCI0.PW32._MAX, PE32)
166 CreateDWordField (CRES, \_SB.PCI0.PW32._LEN, PL32)
167 Store (P0SL, PS32)
168 Store (P0EL, PE32)
169 Store (P0LL, PL32)
170
171 If (LAnd (LEqual (P1SL, 0x00), LEqual (P1SH, 0x00))) {
172 Return (CRES)
173 } Else {
174 //
175 // fixup 64-bit PCI IO window
176 //
177 CreateQWordField (CR64, \_SB.PCI0.PW64._MIN, PS64)
178 CreateQWordField (CR64, \_SB.PCI0.PW64._MAX, PE64)
179 CreateQWordField (CR64, \_SB.PCI0.PW64._LEN, PL64)
180 Store (P1S, PS64)
181 Store (P1E, PE64)
182 Store (P1L, PL64)
183
184 //
185 // add window and return result
186 //
187 ConcatenateResTemplate (CRES, CR64, Local0)
188 Return (Local0)
189 }
190 }
191
192 //
193 // PCI Interrupt Routing Table - PIC Mode Only
194 //
195 Method (_PRT, 0, NotSerialized) {
196 Return (
197 Package () {
198 //
199 // Bus 0; Devices 0 to 15
200 //
201 Package () {0x0000FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},
202 Package () {0x0000FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},
203 Package () {0x0000FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},
204 Package () {0x0000FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},
205
206 //
207 // Bus 0, Device 1, Pin 0 (INTA) is special; it corresponds to the
208 // internally generated SCI (System Control Interrupt), which is
209 // always routed to GSI 9. By setting the third (= Source) field to
210 // zero, we could use the fourth (= Source Index) field to hardwire
211 // the pin to GSI 9 directly.
212 //
213 // That way however, in accordance with the ACPI spec's description
214 // of SCI, the interrupt would be treated as "active low,
215 // shareable, level", and that doesn't match qemu.
216 //
217 // In QemuInstallAcpiMadtTable() [OvmfPkg/AcpiPlatformDxe/Qemu.c]
218 // we install an Interrupt Override Structure for the identity
219 // mapped IRQ#9 / GSI 9 (the corresponding bit being set in
220 // Pcd8259LegacyModeEdgeLevel), which describes the correct
221 // polarity (active high). As a consequence, some OS'en (eg. Linux)
222 // override the default (active low) polarity originating from the
223 // _PRT; others (eg. FreeBSD) don't. Therefore we need a separate
224 // link device just to specify a polarity that matches the MADT.
225 //
226 Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKS, 0x00},
227
228 Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},
229 Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},
230 Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},
231
232 Package () {0x0002FFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},
233 Package () {0x0002FFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},
234 Package () {0x0002FFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},
235 Package () {0x0002FFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},
236
237 Package () {0x0003FFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},
238 Package () {0x0003FFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},
239 Package () {0x0003FFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},
240 Package () {0x0003FFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},
241
242 Package () {0x0004FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},
243 Package () {0x0004FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},
244 Package () {0x0004FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},
245 Package () {0x0004FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},
246
247 Package () {0x0005FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},
248 Package () {0x0005FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},
249 Package () {0x0005FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},
250 Package () {0x0005FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},
251
252 Package () {0x0006FFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},
253 Package () {0x0006FFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},
254 Package () {0x0006FFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},
255 Package () {0x0006FFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},
256
257 Package () {0x0007FFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},
258 Package () {0x0007FFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},
259 Package () {0x0007FFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},
260 Package () {0x0007FFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},
261
262 Package () {0x0008FFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},
263 Package () {0x0008FFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},
264 Package () {0x0008FFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},
265 Package () {0x0008FFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},
266
267 Package () {0x0009FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},
268 Package () {0x0009FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},
269 Package () {0x0009FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},
270 Package () {0x0009FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},
271
272 Package () {0x000AFFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},
273 Package () {0x000AFFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},
274 Package () {0x000AFFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},
275 Package () {0x000AFFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},
276
277 Package () {0x000BFFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},
278 Package () {0x000BFFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},
279 Package () {0x000BFFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},
280 Package () {0x000BFFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00},
281
282 Package () {0x000CFFFF, 0x00, \_SB.PCI0.LPC.LNKD, 0x00},
283 Package () {0x000CFFFF, 0x01, \_SB.PCI0.LPC.LNKA, 0x00},
284 Package () {0x000CFFFF, 0x02, \_SB.PCI0.LPC.LNKB, 0x00},
285 Package () {0x000CFFFF, 0x03, \_SB.PCI0.LPC.LNKC, 0x00},
286
287 Package () {0x000DFFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},
288 Package () {0x000DFFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},
289 Package () {0x000DFFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},
290 Package () {0x000DFFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},
291
292 Package () {0x000EFFFF, 0x00, \_SB.PCI0.LPC.LNKB, 0x00},
293 Package () {0x000EFFFF, 0x01, \_SB.PCI0.LPC.LNKC, 0x00},
294 Package () {0x000EFFFF, 0x02, \_SB.PCI0.LPC.LNKD, 0x00},
295 Package () {0x000EFFFF, 0x03, \_SB.PCI0.LPC.LNKA, 0x00},
296
297 Package () {0x000FFFFF, 0x00, \_SB.PCI0.LPC.LNKC, 0x00},
298 Package () {0x000FFFFF, 0x01, \_SB.PCI0.LPC.LNKD, 0x00},
299 Package () {0x000FFFFF, 0x02, \_SB.PCI0.LPC.LNKA, 0x00},
300 Package () {0x000FFFFF, 0x03, \_SB.PCI0.LPC.LNKB, 0x00}
301 }
302 )
303 }
304
305 //
306 // PCI to ISA Bridge (Bus 0, Device 1, Function 0)
307 // "Low Pin Count"
308 //
309 Device (LPC) {
310 Name (_ADR, 0x00010000)
311
312 //
313 // The SCI cannot be rerouted or disabled with PIRQRC[A:D]; we only
314 // need this link device in order to specify the polarity.
315 //
316 Device (LNKS) {
317 Name (_HID, EISAID("PNP0C0F"))
318 Name (_UID, 0)
319
320 Name (_STA, 0xB) // 0x1: device present
321 // 0x2: enabled and decoding resources
322 // 0x8: functioning properly
323
324 Method (_SRS, 1, NotSerialized) { /* no-op */ }
325 Method (_DIS, 0, NotSerialized) { /* no-op */ }
326
327 Name (_PRS, ResourceTemplate () {
328 Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { 9 }
329 //
330 // list of IRQs occupied thus far: 9
331 //
332 })
333 Method (_CRS, 0, NotSerialized) { Return (_PRS) }
334 }
335
336 //
337 // PCI Interrupt Routing Configuration Registers, PIRQRC[A:D]
338 //
339 OperationRegion (PRR0, PCI_Config, 0x60, 0x04)
340 Field (PRR0, ANYACC, NOLOCK, PRESERVE) {
341 PIRA, 8,
342 PIRB, 8,
343 PIRC, 8,
344 PIRD, 8
345 }
346
347 //
348 // _STA method for LNKA, LNKB, LNKC, LNKD
349 // Arg0[in]: value of PIRA / PIRB / PIRC / PIRD
350 //
351 Method (PSTA, 1, NotSerialized) {
352 If (And (Arg0, 0x80)) { // disable-bit set?
353 Return (0x9) // "device present" | "functioning properly"
354 } Else {
355 Return (0xB) // same | "enabled and decoding resources"
356 }
357 }
358
359 //
360 // _CRS method for LNKA, LNKB, LNKC, LNKD
361 // Arg0[in]: value of PIRA / PIRB / PIRC / PIRD
362 //
363 Method (PCRS, 1, NotSerialized) {
364 //
365 // create temporary buffer with an Extended Interrupt Descriptor
366 // whose single vector defaults to zero
367 //
368 Name (BUF0, ResourceTemplate () {
369 Interrupt (ResourceConsumer, Level, ActiveHigh, Shared){0}
370 }
371 )
372
373 //
374 // define reference to first interrupt vector in buffer
375 //
376 CreateDWordField (BUF0, 0x05, IRQW)
377
378 //
379 // If the disable-bit is clear, overwrite the default zero vector
380 // with the value in Arg0 (ie. PIRQRC[A:D]). Reserved bits are read
381 // as 0.
382 //
383 If (LNot (And (Arg0, 0x80))) {
384 Store (Arg0, IRQW)
385 }
386 Return (BUF0)
387 }
388
389 //
390 // _PRS resource for LNKA, LNKB, LNKC, LNKD
391 //
392 Name (PPRS, ResourceTemplate () {
393 Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) {5, 10, 11}
394 //
395 // list of IRQs occupied thus far: 9, 5, 10, 11
396 //
397 })
398
399 //
400 // PCI IRQ Link A
401 //
402 Device (LNKA) {
403 Name (_HID, EISAID("PNP0C0F"))
404 Name (_UID, 1)
405
406 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRA)) }
407 Method (_DIS, 0, NotSerialized) {
408 Or (PIRA, 0x80, PIRA) // set disable-bit
409 }
410 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRA)) }
411 Method (_PRS, 0, NotSerialized) { Return (PPRS) }
412 Method (_SRS, 1, NotSerialized) {
413 CreateDWordField (Arg0, 0x05, IRQW)
414 Store (IRQW, PIRA)
415 }
416 }
417
418 //
419 // PCI IRQ Link B
420 //
421 Device (LNKB) {
422 Name (_HID, EISAID("PNP0C0F"))
423 Name (_UID, 2)
424
425 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRB)) }
426 Method (_DIS, 0, NotSerialized) {
427 Or (PIRB, 0x80, PIRB) // set disable-bit
428 }
429 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRB)) }
430 Method (_PRS, 0, NotSerialized) { Return (PPRS) }
431 Method (_SRS, 1, NotSerialized) {
432 CreateDWordField (Arg0, 0x05, IRQW)
433 Store (IRQW, PIRB)
434 }
435 }
436
437 //
438 // PCI IRQ Link C
439 //
440 Device (LNKC) {
441 Name (_HID, EISAID("PNP0C0F"))
442 Name (_UID, 3)
443
444 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRC)) }
445 Method (_DIS, 0, NotSerialized) {
446 Or (PIRC, 0x80, PIRC) // set disable-bit
447 }
448 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRC)) }
449 Method (_PRS, 0, NotSerialized) { Return (PPRS) }
450 Method (_SRS, 1, NotSerialized) {
451 CreateDWordField (Arg0, 0x05, IRQW)
452 Store (IRQW, PIRC)
453 }
454 }
455
456 //
457 // PCI IRQ Link D
458 //
459 Device (LNKD) {
460 Name (_HID, EISAID("PNP0C0F"))
461 Name (_UID, 4)
462
463 Method (_STA, 0, NotSerialized) { Return (PSTA (PIRD)) }
464 Method (_DIS, 0, NotSerialized) {
465 Or (PIRD, 0x80, PIRD) // set disable-bit
466 }
467 Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRD)) }
468 Method (_PRS, 0, NotSerialized) { Return (PPRS) }
469 Method (_SRS, 1, NotSerialized) {
470 CreateDWordField (Arg0, 0x05, IRQW)
471 Store (IRQW, PIRD)
472 }
473 }
474
475 //
476 // Programmable Interrupt Controller (PIC)
477 //
478 Device(PIC) {
479 Name (_HID, EISAID ("PNP0000"))
480 Name (_CRS, ResourceTemplate () {
481 IO (Decode16, 0x020, 0x020, 0x00, 0x02)
482 IO (Decode16, 0x0A0, 0x0A0, 0x00, 0x02)
483 IO (Decode16, 0x4D0, 0x4D0, 0x00, 0x02)
484 IRQNoFlags () {2}
485 //
486 // list of IRQs occupied thus far: 9, 5, 10, 11, 2
487 //
488 })
489 }
490
491 //
492 // ISA DMA
493 //
494 Device (DMAC) {
495 Name (_HID, EISAID ("PNP0200"))
496 Name (_CRS, ResourceTemplate () {
497 IO (Decode16, 0x00, 0x00, 0, 0x10)
498 IO (Decode16, 0x81, 0x81, 0, 0x03)
499 IO (Decode16, 0x87, 0x87, 0, 0x01)
500 IO (Decode16, 0x89, 0x89, 0, 0x03)
501 IO (Decode16, 0x8f, 0x8f, 0, 0x01)
502 IO (Decode16, 0xc0, 0xc0, 0, 0x20)
503 DMA (Compatibility, NotBusMaster, Transfer8) {4}
504 })
505 }
506
507 //
508 // 8254 Timer
509 //
510 Device(TMR) {
511 Name(_HID,EISAID("PNP0100"))
512 Name(_CRS, ResourceTemplate () {
513 IO (Decode16, 0x40, 0x40, 0x00, 0x04)
514 IRQNoFlags () {0}
515 //
516 // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0
517 //
518 })
519 }
520
521 //
522 // Real Time Clock
523 //
524 Device (RTC) {
525 Name (_HID, EISAID ("PNP0B00"))
526 Name (_CRS, ResourceTemplate () {
527 IO (Decode16, 0x70, 0x70, 0x00, 0x02)
528 IRQNoFlags () {8}
529 //
530 // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8
531 //
532 })
533 }
534
535 //
536 // PCAT Speaker
537 //
538 Device(SPKR) {
539 Name (_HID, EISAID("PNP0800"))
540 Name (_CRS, ResourceTemplate () {
541 IO (Decode16, 0x61, 0x61, 0x01, 0x01)
542 })
543 }
544
545 //
546 // Floating Point Coprocessor
547 //
548 Device(FPU) {
549 Name (_HID, EISAID("PNP0C04"))
550 Name (_CRS, ResourceTemplate () {
551 IO (Decode16, 0xF0, 0xF0, 0x00, 0x10)
552 IRQNoFlags () {13}
553 //
554 // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8, 13
555 //
556 })
557 }
558
559 //
560 // Generic motherboard devices and pieces that don't fit anywhere else
561 //
562 Device(XTRA) {
563 Name (_HID, EISAID ("PNP0C02"))
564 Name (_UID, 0x01)
565 Name (_CRS, ResourceTemplate () {
566 IO (Decode16, 0x010, 0x010, 0x00, 0x10)
567 IO (Decode16, 0x022, 0x022, 0x00, 0x1E)
568 IO (Decode16, 0x044, 0x044, 0x00, 0x1C)
569 IO (Decode16, 0x062, 0x062, 0x00, 0x02)
570 IO (Decode16, 0x065, 0x065, 0x00, 0x0B)
571 IO (Decode16, 0x072, 0x072, 0x00, 0x0E)
572 IO (Decode16, 0x080, 0x080, 0x00, 0x01)
573 IO (Decode16, 0x084, 0x084, 0x00, 0x03)
574 IO (Decode16, 0x088, 0x088, 0x00, 0x01)
575 IO (Decode16, 0x08c, 0x08c, 0x00, 0x03)
576 IO (Decode16, 0x090, 0x090, 0x00, 0x10)
577 IO (Decode16, 0x0A2, 0x0A2, 0x00, 0x1E)
578 IO (Decode16, 0x0E0, 0x0E0, 0x00, 0x10)
579 IO (Decode16, 0x1E0, 0x1E0, 0x00, 0x10)
580 IO (Decode16, 0x160, 0x160, 0x00, 0x10)
581 IO (Decode16, 0x278, 0x278, 0x00, 0x08)
582 IO (Decode16, 0x370, 0x370, 0x00, 0x02)
583 IO (Decode16, 0x378, 0x378, 0x00, 0x08)
584 IO (Decode16, 0x402, 0x402, 0x00, 0x01) // QEMU debug console, should use FixedPcdGet16 (PcdDebugIoPort)
585 IO (Decode16, 0x440, 0x440, 0x00, 0x10)
586 IO (Decode16, 0x678, 0x678, 0x00, 0x08)
587 IO (Decode16, 0x778, 0x778, 0x00, 0x08)
588 IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK
589 IO (Decode16, 0xb000, 0xb000, 0x00, 0x40) // PMBLK1
590 Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC
591 Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) // LAPIC
592 })
593 }
594
595 //
596 // PS/2 Keyboard and PC/AT Enhanced Keyboard 101/102
597 //
598 Device (PS2K) {
599 Name (_HID, EISAID ("PNP0303"))
600 Name (_CID, EISAID ("PNP030B"))
601 Name(_CRS,ResourceTemplate() {
602 IO (Decode16, 0x60, 0x60, 0x00, 0x01)
603 IO (Decode16, 0x64, 0x64, 0x00, 0x01)
604 IRQNoFlags () {1}
605 //
606 // list of IRQs occupied thus far: 9, 5, 10, 11, 2, 0, 8, 13, 1
607 //
608 })
609 }
610
611 //
612 // PS/2 Mouse and Microsoft Mouse
613 //
614 Device (PS2M) { // PS/2 stype mouse port
615 Name (_HID, EISAID ("PNP0F03"))
616 Name (_CID, EISAID ("PNP0F13"))
617 Name (_CRS, ResourceTemplate() {
618 IRQNoFlags () {12}
619 //
620 // list of IRQs occupied thus far:
621 // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12
622 //
623 })
624 }
625
626 //
627 // UART Serial Port - COM1
628 //
629 Device (UAR1) {
630 Name (_HID, EISAID ("PNP0501"))
631 Name (_DDN, "COM1")
632 Name (_UID, 0x01)
633 Name(_CRS,ResourceTemplate() {
634 IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08)
635 IRQ (Edge, ActiveHigh, Exclusive, ) {4}
636 //
637 // list of IRQs occupied thus far:
638 // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4
639 //
640 })
641 }
642
643 //
644 // UART Serial Port - COM2
645 //
646 Device (UAR2) {
647 Name (_HID, EISAID ("PNP0501"))
648 Name (_DDN, "COM2")
649 Name (_UID, 0x02)
650 Name(_CRS,ResourceTemplate() {
651 IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08)
652 IRQ (Edge, ActiveHigh, Exclusive, ) {3}
653 //
654 // list of IRQs occupied thus far:
655 // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3
656 //
657 })
658 }
659
660 //
661 // Floppy Disk Controller
662 //
663 Device (FDC) {
664 Name (_HID, EISAID ("PNP0700"))
665 Name (_CRS,ResourceTemplate() {
666 IO (Decode16, 0x3F0, 0x3F0, 0x01, 0x06)
667 IO (Decode16, 0x3F7, 0x3F7, 0x01, 0x01)
668 IRQNoFlags () {6}
669 //
670 // list of IRQs occupied thus far:
671 // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3, 6
672 //
673 DMA (Compatibility, NotBusMaster, Transfer8) {2}
674 })
675 }
676
677 //
678 // parallel port -- no DMA for now
679 //
680 Device (PAR1) {
681 Name (_HID, EISAID ("PNP0400"))
682 Name (_DDN, "LPT1")
683 Name (_UID, 0x01)
684 Name(_CRS, ResourceTemplate() {
685 IO (Decode16, 0x0378, 0x0378, 0x00, 0x08)
686 IRQNoFlags () {7}
687 //
688 // list of IRQs occupied thus far:
689 // 9, 5, 10, 11, 2, 0, 8, 13, 1, 12, 4, 3, 6, 7
690 // in order:
691 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
692 //
693 })
694 }
695 }
696 }
697 }
698}