| Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame^] | 1 | /*++
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| 2 |
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| 3 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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| 4 |
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| 5 | This program and the accompanying materials are licensed and made available under
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| 6 | the terms and conditions of the BSD License that accompanies this distribution.
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| 7 | The full text of the license may be found at
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| 8 | http://opensource.org/licenses/bsd-license.php.
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| 9 |
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| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 12 |
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| 13 |
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| 14 |
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| 15 | Module Name:
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| 16 |
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| 17 | Facp.c
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| 18 |
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| 19 |
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| 20 | Abstract: The fixed ACPI description Table (FADT) Structure
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| 21 |
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| 22 |
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| 23 | --*/
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| 24 | #ifdef ECP_FLAG
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| 25 | #include "EDKIIGlueDxe.h"
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| 26 | #else
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| 27 | #include <PiDxe.h>
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| 28 | #endif
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| 29 | #include <IndustryStandard/Acpi50.h>
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| 30 | #include "AcpiTablePlatform.h"
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| 31 |
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| 32 | EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
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| 33 | {
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| 34 | EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
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| 35 | sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),
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| 36 | EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
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| 37 | 0, // to make sum of entire table == 0
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| 38 | EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field
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| 39 | EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
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| 40 | EFI_ACPI_OEM_REVISION, // OEM revision number
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| 41 | EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
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| 42 | EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
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| 43 | },
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| 44 | 0, // Physical addesss of FACS
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| 45 | 0, // Physical address of DSDT
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| 46 | INT_MODEL, // System Interrupt Model (ignored in 2k and later, must be 0 for 98)
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| 47 | PM_PROFILE, // Preferred PM Profile
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| 48 | SCI_INT_VECTOR, // System vector of SCI interrupt
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| 49 | SMI_CMD_IO_PORT, // Port address of SMI command port
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| 50 | ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
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| 51 | ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
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| 52 | S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
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| 53 | PSTATE_CNT, // PState control
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| 54 | PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
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| 55 | PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk
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| 56 | PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
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| 57 | PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk
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| 58 | PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk
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| 59 | PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk
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| 60 | GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk
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| 61 | GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk
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| 62 | PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
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| 63 | PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
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| 64 | PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk
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| 65 | PM_TM_LEN, // Byte Length of ports at pm_tm_blk
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| 66 | GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
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| 67 | GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
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| 68 | GPE1_BASE, // offset in gpe model where gpe1 events start
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| 69 | CST_CNT, // _CST support
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| 70 | P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
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| 71 | P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
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| 72 | FLUSH_SIZE, // Size of area read to flush caches
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| 73 | FLUSH_STRIDE, // Stride used in flushing caches
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| 74 | DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
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| 75 | DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
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| 76 | DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
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| 77 | MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
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| 78 | CENTURY, // index to century in RTC CMOS RAM
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| 79 | IAPC_BOOT_ARCH, // IA-PCI Boot Architecture Flag
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| 80 | RESERVED, // reserved
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| 81 | FLAG,
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| 82 | {
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| 83 | EFI_ACPI_5_0_SYSTEM_IO,
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| 84 | 8,
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| 85 | 0,
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| 86 | 0,
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| 87 | 0xCF9
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| 88 | },
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| 89 | 0x06, // Hardware reset value
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| 90 | 0, 0, 0, // Reserved
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| 91 | 0, // XFirmwareCtrl
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| 92 | 0, // XDsdt
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| 93 | //
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| 94 | // X_PM1a Event Register Block
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| 95 | //
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| 96 | EFI_ACPI_5_0_SYSTEM_IO,
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| 97 | 0x20,
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| 98 | 0x00,
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| 99 | EFI_ACPI_3_0_DWORD,
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| 100 | PM1a_EVT_BLK,
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| 101 |
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| 102 | //
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| 103 | // X_PM1b Event Register Block
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| 104 | //
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| 105 | EFI_ACPI_5_0_SYSTEM_IO,
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| 106 | 0x00,
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| 107 | 0x00,
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| 108 | EFI_ACPI_RESERVED_BYTE,
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| 109 | PM1b_EVT_BLK,
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| 110 |
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| 111 | //
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| 112 | // X_PM1a Control Register Block
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| 113 | //
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| 114 | EFI_ACPI_5_0_SYSTEM_IO,
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| 115 | 0x10,
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| 116 | 0x00,
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| 117 | EFI_ACPI_3_0_WORD,
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| 118 | PM1a_CNT_BLK,
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| 119 |
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| 120 | //
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| 121 | // X_PM1b Control Register Block
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| 122 | //
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| 123 | EFI_ACPI_5_0_SYSTEM_IO,
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| 124 | 0x00,
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| 125 | 0x00,
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| 126 | EFI_ACPI_RESERVED_BYTE,
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| 127 | PM1b_CNT_BLK,
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| 128 |
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| 129 | //
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| 130 | // X_PM2 Control Register Block
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| 131 | //
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| 132 | EFI_ACPI_5_0_SYSTEM_IO,
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| 133 | 0x08,
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| 134 | 0x00,
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| 135 | EFI_ACPI_3_0_BYTE,
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| 136 | PM2_CNT_BLK,
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| 137 |
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| 138 | //
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| 139 | // X_PM Timer Control Register Block
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| 140 | //
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| 141 | EFI_ACPI_5_0_SYSTEM_IO,
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| 142 | 0x20,
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| 143 | 0x00,
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| 144 | EFI_ACPI_3_0_DWORD,
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| 145 | PM_TMR_BLK,
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| 146 |
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| 147 | //
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| 148 | // X_General Purpose Event 0 Register Block
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| 149 | //
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| 150 | EFI_ACPI_5_0_SYSTEM_IO,
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| 151 | 0x80,
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| 152 | 0x00,
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| 153 | EFI_ACPI_RESERVED_BYTE,
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| 154 | GPE0_BLK,
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| 155 |
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| 156 | //
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| 157 | // X_General Purpose Event 1 Register Block
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| 158 | //
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| 159 | EFI_ACPI_5_0_SYSTEM_IO,
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| 160 | 0x00,
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| 161 | 0x00,
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| 162 | EFI_ACPI_RESERVED_BYTE,
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| 163 | GPE1_BLK,
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| 164 |
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| 165 | //
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| 166 | // Sleep Control Register Block
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| 167 | //
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| 168 | EFI_ACPI_5_0_SYSTEM_IO,
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| 169 | 0x08,
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| 170 | 0x00,
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| 171 | EFI_ACPI_RESERVED_BYTE,
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| 172 | 0,
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| 173 |
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| 174 | //
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| 175 | // Sleep Status Register Block
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| 176 | //
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| 177 | EFI_ACPI_5_0_SYSTEM_IO,
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| 178 | 0x08,
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| 179 | 0x00,
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| 180 | EFI_ACPI_RESERVED_BYTE,
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| 181 | 0,
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| 182 | };
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| 183 |
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| 184 | VOID*
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| 185 | ReferenceAcpiTable (
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| 186 | VOID
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| 187 | )
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| 188 | {
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| 189 | //
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| 190 | // Reference the table being generated to prevent the optimizer from
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| 191 | // removing the data structure from the executable
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| 192 | //
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| 193 | return (VOID*)&FACP;
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| 194 | }
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