| Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame^] | 1 | /**************************************************************************;
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| 2 | ;* *;
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| 3 | ;* *;
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| 4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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| 5 | ;* Family of Customer Reference Boards. *;
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| 6 | ;* *;
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| 7 | ;* *;
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| 8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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| 9 | ;
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| 10 | ; This program and the accompanying materials are licensed and made available under
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| 11 | ; the terms and conditions of the BSD License that accompanies this distribution.
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| 12 | ; The full text of the license may be found at
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| 13 | ; http://opensource.org/licenses/bsd-license.php.
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| 14 | ;
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| 15 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 16 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 17 | ;
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| 18 | ;* *;
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| 19 | ;* *;
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| 20 | ;**************************************************************************/
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| 21 |
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| 22 |
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| 23 | // General Purpose Events. This Scope handles the Run-time and
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| 24 | // Wake-time SCIs. The specific method called will be determined by
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| 25 | // the _Lxx value, where xx equals the bit location in the General
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| 26 | // Purpose Event register(s).
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| 27 |
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| 28 | Scope(\_GPE)
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| 29 | {
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| 30 | //
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| 31 | // Software GPE caused the event.
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| 32 | //
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| 33 | Method(_L02)
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| 34 | {
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| 35 | // Clear GPE status bit.
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| 36 | Store(0,GPEC)
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| 37 | //
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| 38 | // Handle DTS Thermal Events.
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| 39 | //
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| 40 | External(DTSE, IntObj)
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| 41 | If(CondRefOf(DTSE))
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| 42 | {
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| 43 | If(LGreaterEqual(DTSE, 0x01))
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| 44 | {
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| 45 | Notify(\_TZ.TZ01,0x80)
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| 46 | }
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| 47 | }
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| 48 | }
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| 49 |
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| 50 | //
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| 51 | // PUNIT SCI event.
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| 52 | //
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| 53 | Method(_L04)
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| 54 | {
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| 55 | // Clear the PUNIT Status Bit.
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| 56 | Store(1, PSCI)
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| 57 | }
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| 58 |
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| 59 |
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| 60 | //
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| 61 | // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).
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| 62 | //
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| 63 | Method(_L05)
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| 64 | {
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| 65 | If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event?
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| 66 | {
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| 67 | \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI
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| 68 | }
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| 69 | }
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| 70 |
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| 71 | //
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| 72 | // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities
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| 73 | // on bus 0 asserts the equivalent of the PME# signal.
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| 74 | //
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| 75 | Method(_L0D, 0)
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| 76 | {
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| 77 | If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES))
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| 78 | {
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| 79 | If(LNotEqual(OSEL, 1))
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| 80 | {
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| 81 | Store(1, \_SB.PCI0.EHC1.PMES) //Clear PME status
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| 82 | Store(0, \_SB.PCI0.EHC1.PMEE) //Disable PME
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| 83 | }
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| 84 | Notify(\_SB.PCI0.EHC1, 0x02)
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| 85 | }
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| 86 | If(LAnd(\_SB.PCI0.XHC1.PMEE, \_SB.PCI0.XHC1.PMES))
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| 87 | {
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| 88 | If(LNotEqual(OSEL, 1))
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| 89 | {
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| 90 | Store(1, \_SB.PCI0.XHC1.PMES) //Clear PME status
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| 91 | Store(0, \_SB.PCI0.XHC1.PMEE) //Disable PME
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| 92 | }
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| 93 | Notify(\_SB.PCI0.XHC1, 0x02)
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| 94 | }
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| 95 | If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES))
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| 96 | {
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| 97 | If(LNotEqual(OSEL, 1))
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| 98 | {
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| 99 | Store(1, \_SB.PCI0.HDEF.PMES) //Clear PME status
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| 100 | Store(0, \_SB.PCI0.HDEF.PMEE) //Disable PME
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| 101 | }
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| 102 | Notify(\_SB.PCI0.HDEF, 0x02)
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| 103 | }
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| 104 | }
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| 105 | }
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