| Vishal Bhoj | 82c8071 | 2015-12-15 21:13:33 +0530 | [diff] [blame^] | 1 | /**************************************************************************;
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| 2 | ;* *;
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| 3 | ;* *;
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| 4 | ;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;
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| 5 | ;* Family of Customer Reference Boards. *;
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| 6 | ;* *;
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| 7 | ;* *;
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| 8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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| 9 | ;
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| 10 | ; This program and the accompanying materials are licensed and made available under
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| 11 | ; the terms and conditions of the BSD License that accompanies this distribution.
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| 12 | ; The full text of the license may be found at
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| 13 | ; http://opensource.org/licenses/bsd-license.php.
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| 14 | ;
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| 15 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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| 16 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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| 17 | ;
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| 18 | ;* *;
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| 19 | ;* *;
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| 20 | ;**************************************************************************/
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| 21 |
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| 22 | Name(PMBS, 0x400) // ASL alias for ACPI I/O base address.
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| 23 | Name(SMIP, 0xb2) // I/O port to trigger SMI
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| 24 | Name(GPBS, 0x500) // GPIO Register Block address
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| 25 | Name(APCB, 0xfec00000) // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled
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| 26 | Name(APCL, 0x1000) // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded
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| 27 | Name(PFDR, 0xfed03034) // PMC Function Disable Register
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| 28 | Name(PMCB, 0xfed03000) // PMC Base Address
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| 29 | Name(PCLK, 0xfed03060) // PMC Clock Control Register
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| 30 | Name(PUNB, 0xfed05000) // PUNIT Base Address
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| 31 | Name(IBAS, 0xfed08000) // ILB Base Address
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| 32 | Name(SRCB, 0xfed1c000) // RCBA (Root Complex Base Address)
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| 33 | Name(SRCL, 0x1000) // RCBA length
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| 34 | Name(HPTB, 0xfed00000) // Same as HPET_BASE_ADDRESS for ASL use
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| 35 | Name(PEBS, 0xe0000000) // PCIe Base
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| 36 | Name(PELN, 0x10000000) //
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| 37 | Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code.
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| 38 | Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code.
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| 39 | Name(SDGV, 0x1c) // UHCI Controller HOST_ALERT's bit offset within the GPE block. GPIO[0:15] corresponding to GPE[16:31]
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| 40 | Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control
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| 41 | Name(SHPC, 0x0) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control
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| 42 | Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control
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| 43 | Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control
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| 44 | Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control
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| 45 |
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