| /* |
| * Device Tree Source for UniPhier PH1-LD20 SoC |
| * |
| * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ X11 |
| */ |
| |
| /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ |
| |
| / { |
| compatible = "socionext,ph1-ld20"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-parent = <&gic>; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu2>; |
| }; |
| core1 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a72", "arm,armv8"; |
| reg = <0 0x000>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0x80000000>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a72", "arm,armv8"; |
| reg = <0 0x001>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0x80000000>; |
| }; |
| |
| cpu2: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0 0x100>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0x80000000>; |
| }; |
| |
| cpu3: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0 0x101>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0x80000000>; |
| }; |
| }; |
| |
| clocks { |
| refclk: ref { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <25000000>; |
| }; |
| |
| i2c_clk: i2c_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <50000000>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 13 4>, |
| <1 14 4>, |
| <1 11 4>, |
| <1 10 4>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| u-boot,dm-pre-reloc; |
| |
| serial0: serial@54006800 { |
| compatible = "socionext,uniphier-uart"; |
| status = "disabled"; |
| reg = <0x54006800 0x40>; |
| interrupts = <0 33 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart0>; |
| clocks = <&peri_clk 0>; |
| clock-frequency = <58820000>; |
| }; |
| |
| serial1: serial@54006900 { |
| compatible = "socionext,uniphier-uart"; |
| status = "disabled"; |
| reg = <0x54006900 0x40>; |
| interrupts = <0 35 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| clocks = <&peri_clk 1>; |
| clock-frequency = <58820000>; |
| }; |
| |
| serial2: serial@54006a00 { |
| compatible = "socionext,uniphier-uart"; |
| status = "disabled"; |
| reg = <0x54006a00 0x40>; |
| interrupts = <0 37 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| clocks = <&peri_clk 2>; |
| clock-frequency = <58820000>; |
| }; |
| |
| serial3: serial@54006b00 { |
| compatible = "socionext,uniphier-uart"; |
| status = "disabled"; |
| reg = <0x54006b00 0x40>; |
| interrupts = <0 177 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| clocks = <&peri_clk 3>; |
| clock-frequency = <58820000>; |
| }; |
| |
| i2c0: i2c@58780000 { |
| compatible = "socionext,uniphier-fi2c"; |
| status = "disabled"; |
| reg = <0x58780000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 41 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c0>; |
| clocks = <&i2c_clk>; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c1: i2c@58781000 { |
| compatible = "socionext,uniphier-fi2c"; |
| status = "disabled"; |
| reg = <0x58781000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 42 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| clocks = <&i2c_clk>; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c2: i2c@58782000 { |
| compatible = "socionext,uniphier-fi2c"; |
| reg = <0x58782000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 43 4>; |
| clocks = <&i2c_clk>; |
| clock-frequency = <400000>; |
| }; |
| |
| i2c3: i2c@58783000 { |
| compatible = "socionext,uniphier-fi2c"; |
| status = "disabled"; |
| reg = <0x58783000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 44 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| clocks = <&i2c_clk>; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c4: i2c@58784000 { |
| compatible = "socionext,uniphier-fi2c"; |
| status = "disabled"; |
| reg = <0x58784000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 45 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c4>; |
| clocks = <&i2c_clk>; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c5: i2c@58785000 { |
| compatible = "socionext,uniphier-fi2c"; |
| reg = <0x58785000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 25 4>; |
| clocks = <&i2c_clk>; |
| clock-frequency = <400000>; |
| }; |
| |
| system_bus: system-bus@58c00000 { |
| compatible = "socionext,uniphier-system-bus"; |
| status = "disabled"; |
| reg = <0x58c00000 0x400>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_system_bus>; |
| }; |
| |
| smpctrl@59800000 { |
| compatible = "socionext,uniphier-smpctrl"; |
| reg = <0x59801000 0x400>; |
| }; |
| |
| mioctrl@59810000 { |
| compatible = "socionext,uniphier-mioctrl", |
| "simple-mfd", "syscon"; |
| reg = <0x59810000 0x800>; |
| |
| mio_clk: clock { |
| compatible = "socionext,uniphier-ld20-mio-clock"; |
| #clock-cells = <1>; |
| }; |
| |
| mio_rst: reset { |
| compatible = "socionext,uniphier-ld20-mio-reset"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| perictrl@59820000 { |
| compatible = "socionext,uniphier-perictrl", |
| "simple-mfd", "syscon"; |
| reg = <0x59820000 0x200>; |
| |
| peri_clk: clock { |
| compatible = "socionext,uniphier-ld20-peri-clock"; |
| #clock-cells = <1>; |
| }; |
| |
| peri_rst: reset { |
| compatible = "socionext,uniphier-ld20-peri-reset"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| sd: sdhc@5a400000 { |
| compatible = "socionext,uniphier-sdhc"; |
| status = "disabled"; |
| reg = <0x5a400000 0x800>; |
| interrupts = <0 76 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sd>; |
| clocks = <&mio_clk 0>; |
| bus-width = <4>; |
| }; |
| |
| soc-glue@5f800000 { |
| compatible = "socionext,uniphier-soc-glue", |
| "simple-mfd", "syscon"; |
| reg = <0x5f800000 0x2000>; |
| u-boot,dm-pre-reloc; |
| |
| pinctrl: pinctrl { |
| compatible = "socionext,uniphier-ld20-pinctrl"; |
| u-boot,dm-pre-reloc; |
| }; |
| }; |
| |
| aidet@5fc20000 { |
| compatible = "simple-mfd", "syscon"; |
| reg = <0x5fc20000 0x200>; |
| }; |
| |
| gic: interrupt-controller@5fe00000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x5fe00000 0x10000>, /* GICD */ |
| <0x5fe80000 0x80000>; /* GICR */ |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <1 9 4>; |
| }; |
| |
| sysctrl@61840000 { |
| compatible = "socionext,uniphier-sysctrl", |
| "simple-mfd", "syscon"; |
| reg = <0x61840000 0x4000>; |
| |
| sys_clk: clock { |
| compatible = "socionext,uniphier-ld20-clock"; |
| #clock-cells = <1>; |
| }; |
| |
| sys_rst: reset { |
| compatible = "socionext,uniphier-ld20-reset"; |
| #reset-cells = <1>; |
| }; |
| }; |
| }; |
| }; |
| |
| /include/ "uniphier-pinctrl.dtsi" |