| // SPDX-License-Identifier: GPL-2.0+ |
| |
| #include <stm32h7-u-boot.dtsi> |
| |
| &fmc { |
| /* |
| * Memory configuration from sdram datasheet W9825G6KH |
| * first bank is bank@0 |
| * second bank is bank@1 |
| */ |
| bank1: bank@0 { |
| st,sdram-control = /bits/ 8 <NO_COL_9 |
| NO_ROW_13 |
| MWIDTH_16 |
| BANKS_4 |
| CAS_2 |
| SDCLK_3 |
| RD_BURST_EN |
| RD_PIPE_DL_0>; |
| st,sdram-timing = /bits/ 8 <TMRD_2 |
| TXSR_6 |
| TRAS_6 |
| TRC_6 |
| TRP_2 |
| TWR_2 |
| TRCD_2>; |
| st,sdram-refcount = <677>; |
| }; |
| }; |
| |
| &pinctrl { |
| fmc_pins: fmc@0 { |
| pins { |
| pinmux = <STM32_PINMUX('D', 0, AF12)>, |
| <STM32_PINMUX('D', 1, AF12)>, |
| <STM32_PINMUX('D', 8, AF12)>, |
| <STM32_PINMUX('D', 9, AF12)>, |
| <STM32_PINMUX('D',10, AF12)>, |
| <STM32_PINMUX('D',14, AF12)>, |
| <STM32_PINMUX('D',15, AF12)>, |
| |
| <STM32_PINMUX('E', 0, AF12)>, |
| <STM32_PINMUX('E', 1, AF12)>, |
| <STM32_PINMUX('E', 7, AF12)>, |
| <STM32_PINMUX('E', 8, AF12)>, |
| <STM32_PINMUX('E', 9, AF12)>, |
| <STM32_PINMUX('E',10, AF12)>, |
| <STM32_PINMUX('E',11, AF12)>, |
| <STM32_PINMUX('E',12, AF12)>, |
| <STM32_PINMUX('E',13, AF12)>, |
| <STM32_PINMUX('E',14, AF12)>, |
| <STM32_PINMUX('E',15, AF12)>, |
| |
| <STM32_PINMUX('F', 0, AF12)>, |
| <STM32_PINMUX('F', 1, AF12)>, |
| <STM32_PINMUX('F', 2, AF12)>, |
| <STM32_PINMUX('F', 3, AF12)>, |
| <STM32_PINMUX('F', 4, AF12)>, |
| <STM32_PINMUX('F', 5, AF12)>, |
| <STM32_PINMUX('F',11, AF12)>, |
| <STM32_PINMUX('F',12, AF12)>, |
| <STM32_PINMUX('F',13, AF12)>, |
| <STM32_PINMUX('F',14, AF12)>, |
| <STM32_PINMUX('F',15, AF12)>, |
| |
| <STM32_PINMUX('G', 0, AF12)>, |
| <STM32_PINMUX('G', 1, AF12)>, |
| <STM32_PINMUX('G', 2, AF12)>, |
| <STM32_PINMUX('G', 4, AF12)>, |
| <STM32_PINMUX('G', 5, AF12)>, |
| <STM32_PINMUX('G', 8, AF12)>, |
| <STM32_PINMUX('G',15, AF12)>, |
| |
| <STM32_PINMUX('H', 5, AF12)>, |
| <STM32_PINMUX('C', 2, AF12)>, |
| <STM32_PINMUX('C', 3, AF12)>; |
| |
| slew-rate = <3>; |
| }; |
| }; |
| }; |