| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * dts file for Xilinx ZynqMP zc1751-xm015-dc1 |
| * |
| * (C) Copyright 2015 - 2021, Xilinx, Inc. |
| * |
| * Michal Simek <michal.simek@xilinx.com> |
| */ |
| |
| /dts-v1/; |
| |
| #include "zynqmp.dtsi" |
| #include "zynqmp-clk-ccf.dtsi" |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> |
| |
| / { |
| model = "ZynqMP zc1751-xm015-dc1 RevA"; |
| compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; |
| |
| aliases { |
| ethernet0 = &gem3; |
| i2c0 = &i2c1; |
| mmc0 = &sdhci0; |
| mmc1 = &sdhci1; |
| rtc0 = &rtc; |
| serial0 = &uart0; |
| spi0 = &qspi; |
| usb0 = &usb0; |
| }; |
| |
| chosen { |
| bootargs = "earlycon"; |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| memory@0 { |
| device_type = "memory"; |
| reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
| }; |
| |
| clock_si5338_0: clk27 { /* u55 SI5338-GM */ |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <27000000>; |
| }; |
| |
| clock_si5338_2: clk26 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| }; |
| |
| clock_si5338_3: clk150 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <150000000>; |
| }; |
| }; |
| |
| &fpd_dma_chan1 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan2 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan3 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan4 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan5 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan6 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan7 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan8 { |
| status = "okay"; |
| }; |
| |
| &gem3 { |
| status = "okay"; |
| phy-handle = <&phy0>; |
| phy-mode = "rgmii-id"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gem3_default>; |
| phy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| }; |
| |
| &gpio { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpio_default>; |
| }; |
| |
| &gpu { |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| status = "okay"; |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1_default>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; |
| |
| eeprom: eeprom@55 { |
| compatible = "atmel,24c64"; /* 24AA64 */ |
| reg = <0x55>; |
| }; |
| }; |
| |
| &pinctrl0 { |
| status = "okay"; |
| pinctrl_i2c1_default: i2c1-default { |
| mux { |
| groups = "i2c1_9_grp"; |
| function = "i2c1"; |
| }; |
| |
| conf { |
| groups = "i2c1_9_grp"; |
| bias-pull-up; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1-gpio { |
| mux { |
| groups = "gpio0_36_grp", "gpio0_37_grp"; |
| function = "gpio0"; |
| }; |
| |
| conf { |
| groups = "gpio0_36_grp", "gpio0_37_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| }; |
| |
| pinctrl_uart0_default: uart0-default { |
| mux { |
| groups = "uart0_8_grp"; |
| function = "uart0"; |
| }; |
| |
| conf { |
| groups = "uart0_8_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| |
| conf-rx { |
| pins = "MIO34"; |
| bias-high-impedance; |
| }; |
| |
| conf-tx { |
| pins = "MIO35"; |
| bias-disable; |
| }; |
| }; |
| |
| pinctrl_usb0_default: usb0-default { |
| mux { |
| groups = "usb0_0_grp"; |
| function = "usb0"; |
| }; |
| |
| conf { |
| groups = "usb0_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| |
| conf-rx { |
| pins = "MIO52", "MIO53", "MIO55"; |
| bias-high-impedance; |
| }; |
| |
| conf-tx { |
| pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", |
| "MIO60", "MIO61", "MIO62", "MIO63"; |
| bias-disable; |
| }; |
| }; |
| |
| pinctrl_gem3_default: gem3-default { |
| mux { |
| function = "ethernet3"; |
| groups = "ethernet3_0_grp"; |
| }; |
| |
| conf { |
| groups = "ethernet3_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| |
| conf-rx { |
| pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", |
| "MIO75"; |
| bias-high-impedance; |
| low-power-disable; |
| }; |
| |
| conf-tx { |
| pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", |
| "MIO69"; |
| bias-disable; |
| low-power-enable; |
| }; |
| |
| mux-mdio { |
| function = "mdio3"; |
| groups = "mdio3_0_grp"; |
| }; |
| |
| conf-mdio { |
| groups = "mdio3_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| bias-disable; |
| }; |
| }; |
| |
| pinctrl_sdhci0_default: sdhci0-default { |
| mux { |
| groups = "sdio0_0_grp"; |
| function = "sdio0"; |
| }; |
| |
| conf { |
| groups = "sdio0_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| bias-disable; |
| }; |
| |
| mux-cd { |
| groups = "sdio0_cd_0_grp"; |
| function = "sdio0_cd"; |
| }; |
| |
| conf-cd { |
| groups = "sdio0_cd_0_grp"; |
| bias-high-impedance; |
| bias-pull-up; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| |
| mux-wp { |
| groups = "sdio0_wp_0_grp"; |
| function = "sdio0_wp"; |
| }; |
| |
| conf-wp { |
| groups = "sdio0_wp_0_grp"; |
| bias-high-impedance; |
| bias-pull-up; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| }; |
| |
| pinctrl_sdhci1_default: sdhci1-default { |
| mux { |
| groups = "sdio1_0_grp"; |
| function = "sdio1"; |
| }; |
| |
| conf { |
| groups = "sdio1_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| bias-disable; |
| }; |
| |
| mux-cd { |
| groups = "sdio1_cd_0_grp"; |
| function = "sdio1_cd"; |
| }; |
| |
| conf-cd { |
| groups = "sdio1_cd_0_grp"; |
| bias-high-impedance; |
| bias-pull-up; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| |
| mux-wp { |
| groups = "sdio1_wp_0_grp"; |
| function = "sdio1_wp"; |
| }; |
| |
| conf-wp { |
| groups = "sdio1_wp_0_grp"; |
| bias-high-impedance; |
| bias-pull-up; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| }; |
| |
| pinctrl_gpio_default: gpio-default { |
| mux { |
| function = "gpio0"; |
| groups = "gpio0_38_grp"; |
| }; |
| |
| conf { |
| groups = "gpio0_38_grp"; |
| bias-disable; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| }; |
| }; |
| |
| &psgtr { |
| status = "okay"; |
| /* dp, usb3, sata */ |
| clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; |
| clock-names = "ref1", "ref2", "ref3"; |
| }; |
| |
| &qspi { |
| status = "okay"; |
| flash@0 { |
| compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x0>; |
| spi-tx-bus-width = <4>; |
| spi-rx-bus-width = <4>; |
| spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
| partition@0 { /* for testing purpose */ |
| label = "qspi-fsbl-uboot"; |
| reg = <0x0 0x100000>; |
| }; |
| partition@100000 { /* for testing purpose */ |
| label = "qspi-linux"; |
| reg = <0x100000 0x500000>; |
| }; |
| partition@600000 { /* for testing purpose */ |
| label = "qspi-device-tree"; |
| reg = <0x600000 0x20000>; |
| }; |
| partition@620000 { /* for testing purpose */ |
| label = "qspi-rootfs"; |
| reg = <0x620000 0x5E0000>; |
| }; |
| }; |
| }; |
| |
| &rtc { |
| status = "okay"; |
| }; |
| |
| &sata { |
| status = "okay"; |
| /* SATA phy OOB timing settings */ |
| ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; |
| ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; |
| ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
| ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
| ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; |
| ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; |
| ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
| ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
| phy-names = "sata-phy"; |
| phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; |
| }; |
| |
| /* eMMC */ |
| &sdhci0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sdhci0_default>; |
| bus-width = <8>; |
| xlnx,mio-bank = <0>; |
| }; |
| |
| /* SD1 with level shifter */ |
| &sdhci1 { |
| status = "okay"; |
| /* |
| * This property should be removed for supporting UHS mode |
| */ |
| no-1-8-v; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sdhci1_default>; |
| xlnx,mio-bank = <1>; |
| }; |
| |
| &uart0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart0_default>; |
| }; |
| |
| /* ULPI SMSC USB3320 */ |
| &usb0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usb0_default>; |
| phy-names = "usb3-phy"; |
| phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; |
| }; |
| |
| &dwc3_0 { |
| status = "okay"; |
| dr_mode = "host"; |
| snps,usb3_lpm_capable; |
| maximum-speed = "super-speed"; |
| }; |
| |
| &zynqmp_dpdma { |
| status = "okay"; |
| }; |
| |
| &zynqmp_dpsub { |
| status = "okay"; |
| phy-names = "dp-phy0", "dp-phy1"; |
| phys = <&psgtr 1 PHY_TYPE_DP 0 0>, |
| <&psgtr 0 PHY_TYPE_DP 1 1>; |
| }; |