| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * ABB PGGA KMETER1 Device Tree Source |
| * |
| * 2008-2011 DENX Software Engineering GmbH |
| * Copyright (C) 2020 Heiko Schocher <hs@denx.de> |
| */ |
| |
| /dts-v1/; |
| |
| #include "km836x.dtsi" |
| |
| / { |
| model = "KMETER1"; |
| compatible = "ABB,KMETER1"; |
| |
| aliases { |
| ethernet0 = &enet_piggy2; |
| ethernet1 = &enet_estar1; |
| ethernet2 = &enet_estar2; |
| ethernet3 = &enet_eth1; |
| ethernet4 = &enet_eth2; |
| ethernet5 = &enet_eth3; |
| ethernet6 = &enet_eth4; |
| serial0 = &serial0; |
| }; |
| }; |
| |
| &i2c0 { |
| mux@70 { |
| compatible = "nxp,pca9547"; |
| reg = <0x70>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| i2c@1 { |
| reg = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* Inventory EEPROM of the unit itself */ |
| ivm@50 { |
| label = "MAIN_CTRL"; |
| compatible = "dummy"; |
| reg = <0x50>; |
| }; |
| }; |
| |
| i2c@2 { |
| reg = <2>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* Temperature sensors */ |
| temp@48 { |
| label = "Top"; |
| compatible = "national,lm75"; |
| reg = <0x48>; |
| }; |
| |
| temp@49 { |
| label = "Control"; |
| compatible = "national,lm75"; |
| reg = <0x49>; |
| }; |
| |
| temp@4a { |
| label = "Power"; |
| compatible = "national,lm75"; |
| reg = <0x4a>; |
| }; |
| |
| temp@4b { |
| label = "Front"; |
| compatible = "national,lm75"; |
| reg = <0x4b>; |
| }; |
| }; |
| }; |
| }; |
| |
| &serial0 { |
| status = "okay"; |
| }; |
| |
| &par_io { |
| pio_ucc1: ucc_pin@0 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 1 3 0 2 0 /* MDIO */ |
| 0 2 1 0 1 0 /* MDC */ |
| |
| 0 3 1 0 1 0 /* TxD0 */ |
| 0 4 1 0 1 0 /* TxD1 */ |
| 0 5 1 0 1 0 /* TxD2 */ |
| 0 6 1 0 1 0 /* TxD3 */ |
| 0 9 2 0 1 0 /* RxD0 */ |
| 0 10 2 0 1 0 /* RxD1 */ |
| 0 11 2 0 1 0 /* RxD2 */ |
| 0 12 2 0 1 0 /* RxD3 */ |
| 0 7 1 0 1 0 /* TX_EN */ |
| 0 8 1 0 1 0 /* TX_ER */ |
| 0 15 2 0 1 0 /* RX_DV */ |
| 0 16 2 0 1 0 /* RX_ER */ |
| 0 0 2 0 1 0 /* RX_CLK */ |
| 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ |
| 2 8 2 0 1 0 /* GTX125 - CLK9 */ |
| >; |
| }; |
| |
| pio_ucc2: ucc_pin@1 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 1 3 0 2 0 /* MDIO */ |
| 0 2 1 0 1 0 /* MDC */ |
| |
| 0 17 1 0 1 0 /* TxD0 */ |
| 0 18 1 0 1 0 /* TxD1 */ |
| 0 19 1 0 1 0 /* TxD2 */ |
| 0 20 1 0 1 0 /* TxD3 */ |
| 0 23 2 0 1 0 /* RxD0 */ |
| 0 24 2 0 1 0 /* RxD1 */ |
| 0 25 2 0 1 0 /* RxD2 */ |
| 0 26 2 0 1 0 /* RxD3 */ |
| 0 21 1 0 1 0 /* TX_EN */ |
| 0 22 1 0 1 0 /* TX_ER */ |
| 0 29 2 0 1 0 /* RX_DV */ |
| 0 30 2 0 1 0 /* RX_ER */ |
| 0 31 2 0 1 0 /* RX_CLK */ |
| 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ |
| 2 3 2 0 1 0 /* GTX125 - CLK4 */ |
| >; |
| }; |
| |
| pio_ucc4: ucc_pin@3 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 1 3 0 2 0 /* MDIO */ |
| 0 2 1 0 1 0 /* MDC */ |
| |
| 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ |
| 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ |
| 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ |
| 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ |
| 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ |
| 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ |
| 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ |
| |
| 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ |
| >; |
| }; |
| |
| pio_ucc5: ucc_pin@4 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 1 3 0 2 0 /* MDIO */ |
| 0 2 1 0 1 0 /* MDC */ |
| |
| 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ |
| 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ |
| 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ |
| 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ |
| 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ |
| 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ |
| 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ |
| >; |
| }; |
| |
| pio_ucc6: ucc_pin@5 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 1 3 0 2 0 /* MDIO */ |
| 0 2 1 0 1 0 /* MDC */ |
| |
| 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ |
| 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ |
| 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ |
| 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ |
| 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ |
| 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ |
| 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ |
| >; |
| }; |
| |
| pio_ucc7: ucc_pin@6 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 1 3 0 2 0 /* MDIO */ |
| 0 2 1 0 1 0 /* MDC */ |
| |
| 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ |
| 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ |
| 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ |
| 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ |
| 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ |
| 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ |
| 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ |
| >; |
| }; |
| |
| pio_ucc8: ucc_pin@7 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 1 3 0 2 0 /* MDIO */ |
| 0 2 1 0 1 0 /* MDC */ |
| |
| 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ |
| 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ |
| 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ |
| 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ |
| 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ |
| 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ |
| 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ |
| |
| 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ |
| >; |
| }; |
| |
| pio_spi: spi_pin@01 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */ |
| 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */ |
| >; |
| }; |
| |
| /* UCC3 as HDLC controller for ICN */ |
| pio5: ucc_pin@02 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 1 0 1 0 1 0 /* TxD0 */ |
| 1 6 2 0 1 0 /* RxD0 */ |
| 1 12 2 0 1 0 /* CTS */ |
| 2 11 2 0 1 0 /* TX-CLK12 */ |
| >; |
| }; |
| |
| pio_tdm: tdm_pin@00 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| /* TDMa */ |
| 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ |
| 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ |
| 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ |
| 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ |
| /* TDMb */ |
| 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ |
| 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ |
| 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ |
| 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ |
| /* TDMc */ |
| 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ |
| 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ |
| 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ |
| 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ |
| /* TDMd */ |
| 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ |
| 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ |
| 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ |
| 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ |
| /* TDMe */ |
| 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ |
| 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ |
| 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ |
| 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ |
| /* TDMf */ |
| 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ |
| 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ |
| 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ |
| 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ |
| /* TDMg */ |
| 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ |
| 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ |
| 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ |
| 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ |
| /* TDMh */ |
| 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ |
| 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ |
| 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ |
| 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ |
| /* RxTxClk0/1 */ |
| 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ |
| 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ |
| /* RxTxSync0/1 */ |
| 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ |
| 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ |
| }; |
| }; |
| |
| &qe { |
| /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ |
| enet_estar1: ucc@2000 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| cell-index = <1>; |
| reg = <0x2000 0x200>; |
| interrupts = <32>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk9"; |
| phy-handle = <&phy_estar1>; |
| phy-connection-type = "rgmii-id"; |
| pio-handle = <&pio_ucc1>; |
| }; |
| |
| /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ |
| enet_estar2: ucc@3000 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| cell-index = <2>; |
| reg = <0x3000 0x200>; |
| interrupts = <33>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk4"; |
| phy-handle = <&phy_estar2>; |
| phy-connection-type = "rgmii-id"; |
| pio-handle = <&pio_ucc2>; |
| }; |
| |
| /* Piggy2 (UCC4, MDIO 0x00, RMII) */ |
| enet_piggy2: ucc@3200 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| cell-index = <4>; |
| reg = <0x3200 0x200>; |
| interrupts = <35>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk17"; |
| phy-handle = <&phy_piggy2>; |
| phy-connection-type = "rmii"; |
| pio-handle = <&pio_ucc4>; |
| }; |
| |
| /* Eth-1 (UCC5, MDIO 0x08, RMII) */ |
| enet_eth1: ucc@2400 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| cell-index = <5>; |
| reg = <0x2400 0x200>; |
| interrupts = <40>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk16"; |
| phy-handle = <&phy_eth1>; |
| phy-connection-type = "rmii"; |
| pio-handle = <&pio_ucc5>; |
| }; |
| |
| /* Eth-2 (UCC6, MDIO 0x09, RMII) */ |
| enet_eth2: ucc@3400 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| cell-index = <6>; |
| reg = <0x3400 0x200>; |
| interrupts = <41>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk16"; |
| phy-handle = <&phy_eth2>; |
| phy-connection-type = "rmii"; |
| pio-handle = <&pio_ucc6>; |
| }; |
| |
| /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ |
| enet_eth3: ucc@2600 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| cell-index = <7>; |
| reg = <0x2600 0x200>; |
| interrupts = <42>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk16"; |
| phy-handle = <&phy_eth3>; |
| phy-connection-type = "rmii"; |
| pio-handle = <&pio_ucc7>; |
| }; |
| |
| /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ |
| enet_eth4: ucc@3600 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| cell-index = <8>; |
| reg = <0x3600 0x200>; |
| interrupts = <43>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk16"; |
| phy-handle = <&phy_eth4>; |
| phy-connection-type = "rmii"; |
| pio-handle = <&pio_ucc8>; |
| }; |
| |
| mdio@3320 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x3320 0x18>; |
| compatible = "fsl,ucc-mdio"; |
| |
| /* Piggy2 (UCC4, MDIO 0x00, RMII) */ |
| phy_piggy2: ethernet-phy@0 { |
| reg = <0x0>; |
| }; |
| |
| /* Eth-1 (UCC5, MDIO 0x08, RMII) */ |
| phy_eth1: ethernet-phy@8 { |
| reg = <0x08>; |
| }; |
| |
| /* Eth-2 (UCC6, MDIO 0x09, RMII) */ |
| phy_eth2: ethernet-phy@9 { |
| reg = <0x09>; |
| }; |
| |
| /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ |
| phy_eth3: ethernet-phy@a { |
| reg = <0x0a>; |
| }; |
| |
| /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ |
| phy_eth4: ethernet-phy@b { |
| reg = <0x0b>; |
| }; |
| |
| /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ |
| phy_estar1: ethernet-phy@10 { |
| interrupt-parent = <&ipic>; |
| interrupts = <17 0x8>; |
| reg = <0x10>; |
| }; |
| |
| /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ |
| phy_estar2: ethernet-phy@11 { |
| interrupt-parent = <&ipic>; |
| interrupts = <18 0x8>; |
| reg = <0x11>; |
| }; |
| }; |
| }; |
| |
| &localbus { |
| ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ |
| 1 0 0xe8000000 0x01000000 /* LB 1 */ |
| 3 0 0xa0000000 0x10000000>; /* LB 3 */ |
| |
| flash@0,0 { |
| compatible = "cfi-flash"; |
| reg = <0 0 0x04000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| bank-width = <2>; |
| partition@0 { /* 768KB */ |
| label = "u-boot"; |
| reg = <0 0xC0000>; |
| }; |
| partition@c0000 { /* 128KB */ |
| label = "env"; |
| reg = <0xC0000 0x20000>; |
| }; |
| partition@e0000 { /* 128KB */ |
| label = "envred"; |
| reg = <0xE0000 0x20000>; |
| }; |
| partition@100000 { /* 64512KB */ |
| label = "ubi0"; |
| reg = <0x100000 0x3F00000>; |
| }; |
| }; |
| }; |
| |
| #include "kmeter1-uboot.dtsi" |