arm: a37xx: Update DTS files to version from upstream Linux kernel
This change updates all Armada 37xx DTS files to version which is used by
Linux kernel v5.18.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 8ac481c..9fa6457 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 37xx family of SoCs.
*
@@ -5,48 +6,9 @@
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/comphy/comphy_data.h>
-#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 37xx SoC";
@@ -57,15 +19,32 @@
aliases {
serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * The PSCI firmware region depicted below is the default one
+ * and should be updated by the bootloader.
+ */
+ psci-area@4000000 {
+ reg = <0 0x4000000 0 0x200000>;
+ no-map;
+ };
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0>;
+ clocks = <&nb_periph_clk 16>;
enable-method = "psci";
};
};
@@ -77,14 +56,15 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
@@ -93,53 +73,123 @@
#size-cells = <2>;
ranges;
- internal-regs {
+ internal-regs@d0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
/* 32M internal register @ 0xd000_0000 */
ranges = <0x0 0x0 0xd0000000 0x2000000>;
- uart0: serial@12000 {
- compatible = "marvell,armada-3700-uart";
- reg = <0x12000 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ wdt: watchdog@8300 {
+ compatible = "marvell,armada-3700-wdt";
+ reg = <0x8300 0x40>;
+ marvell,system-controller = <&cpu_misc>;
+ clocks = <&xtalclk>;
+ };
+
+ cpu_misc: system-controller@d000 {
+ compatible = "marvell,armada-3700-cpu-misc",
+ "syscon";
+ reg = <0xd000 0x1000>;
+ };
+
+ spi0: spi@10600 {
+ compatible = "marvell,armada-3700-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10600 0xA00>;
+ clocks = <&nb_periph_clk 7>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <4>;
status = "disabled";
};
- wdt: watchdog-timer@8300 {
- compatible = "marvell,armada-3700-wdt";
- reg = <0x8300 0x40>;
+ i2c0: i2c@11000 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11000 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&nb_periph_clk 10>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11080 {
+ compatible = "marvell,armada-3700-i2c";
+ reg = <0x11080 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&nb_periph_clk 9>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ avs: avs@11500 {
+ compatible = "marvell,armada-3700-avs",
+ "syscon";
+ reg = <0x11500 0x40>;
+ };
+
+ uart0: serial@12000 {
+ compatible = "marvell,armada-3700-uart";
+ reg = <0x12000 0x18>;
+ clocks = <&xtalclk>;
+ interrupts =
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uart-sum", "uart-tx", "uart-rx";
+ status = "disabled";
+ };
+
+ uart1: serial@12200 {
+ compatible = "marvell,armada-3700-uart-ext";
+ reg = <0x12200 0x30>;
+ clocks = <&xtalclk>;
+ interrupts =
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uart-tx", "uart-rx";
+ status = "disabled";
};
nb_periph_clk: nb-periph-clk@13000 {
- compatible = "marvell,armada-3700-periph-clock-nb";
+ compatible = "marvell,armada-3700-periph-clock-nb",
+ "syscon";
reg = <0x13000 0x100>;
- clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
+ clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
+ <&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
sb_periph_clk: sb-periph-clk@18000 {
compatible = "marvell,armada-3700-periph-clock-sb";
reg = <0x18000 0x100>;
- clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
+ clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
+ <&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
tbg: tbg@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x100>;
+ clocks = <&xtalclk>;
#clock-cells = <1>;
};
- pinctrl_nb: pinctrl-nb@13800 {
+ pinctrl_nb: pinctrl@13800 {
compatible = "marvell,armada3710-nb-pinctrl",
- "syscon", "simple-mfd";
+ "syscon", "simple-mfd";
reg = <0x13800 0x100>, <0x13C00 0x20>;
- gpionb: gpionb {
+ /* MPP1[19:0] */
+ gpionb: gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_nb 0 0 36>;
gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
interrupts =
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
@@ -153,7 +203,12 @@
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ xtalclk: xtal-clk {
+ compatible = "marvell,armada-3700-xtal-clock";
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
};
spi_quad_pins: spi-quad-pins {
@@ -161,6 +216,11 @@
function = "spi";
};
+ spi_cs1_pins: spi-cs1-pins {
+ groups = "spi_cs1";
+ function = "spi";
+ };
+
i2c1_pins: i2c1-pins {
groups = "i2c1";
function = "i2c";
@@ -187,14 +247,54 @@
};
};
- pinctrl_sb: pinctrl-sb@18800 {
+ nb_pm: syscon@14000 {
+ compatible = "marvell,armada-3700-nb-pm",
+ "syscon";
+ reg = <0x14000 0x60>;
+ };
+
+ comphy: phy@18300 {
+ compatible = "marvell,comphy-a3700";
+ reg = <0x18300 0x300>,
+ <0x1F000 0x400>,
+ <0x5C000 0x400>,
+ <0xe0178 0x8>;
+ reg-names = "comphy",
+ "lane1_pcie_gbe",
+ "lane0_usb3_gbe",
+ "lane2_sata_usb3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&xtalclk>;
+ clock-names = "xtal";
+
+ comphy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ comphy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ comphy2: phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
+ pinctrl_sb: pinctrl@18800 {
compatible = "marvell,armada3710-sb-pinctrl",
- "syscon", "simple-mfd";
+ "syscon", "simple-mfd";
reg = <0x18800 0x100>, <0x18C00 0x20>;
- gpiosb: gpiosb {
+ /* MPP2[23:0] */
+ gpiosb: gpio {
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_sb 0 0 30>;
gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
@@ -218,30 +318,92 @@
function = "sdio";
};
- pcie_pins: pcie-pins {
- groups = "pcie1";
+ pcie_reset_pins: pcie-reset-pins {
+ groups = "pcie1"; /* this actually controls "pcie1_reset" */
function = "gpio";
};
+
+ pcie_clkreq_pins: pcie-clkreq-pins {
+ groups = "pcie1_clkreq";
+ function = "pcie";
+ };
+ };
+
+ eth0: ethernet@30000 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x30000 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sb_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@40000 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x40000 0x4000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sb_periph_clk 7>;
+ status = "disabled";
};
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
reg = <0x58000 0x4000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,usb-misc-reg = <&usb32_syscon>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sb_periph_clk 12>;
+ phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
+ phy-names = "usb3-phy", "usb2-utmi-otg-phy";
status = "disabled";
};
+ usb2_utmi_otg_phy: phy@5d000 {
+ compatible = "marvell,a3700-utmi-otg-phy";
+ reg = <0x5d000 0x800>;
+ marvell,usb-misc-reg = <&usb32_syscon>;
+ #phy-cells = <0>;
+ };
+
+ usb32_syscon: system-controller@5d800 {
+ compatible = "marvell,armada-3700-usb2-host-device-misc",
+ "syscon";
+ reg = <0x5d800 0x800>;
+ };
+
usb2: usb@5e000 {
compatible = "marvell,armada-3700-ehci";
- reg = <0x5e000 0x450>;
+ reg = <0x5e000 0x1000>;
+ marvell,usb-misc-reg = <&usb2_syscon>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_utmi_host_phy>;
+ phy-names = "usb2-utmi-host-phy";
status = "disabled";
};
+ usb2_utmi_host_phy: phy@5f000 {
+ compatible = "marvell,a3700-utmi-host-phy";
+ reg = <0x5f000 0x800>;
+ marvell,usb-misc-reg = <&usb2_syscon>;
+ #phy-cells = <0>;
+ };
+
+ usb2_syscon: system-controller@5f800 {
+ compatible = "marvell,armada-3700-usb2-host-misc",
+ "syscon";
+ reg = <0x5f800 0x800>;
+ };
+
xor@60900 {
compatible = "marvell,armada-3700-xor";
- reg = <0x60900 0x100
- 0x60b00 0x100>;
+ reg = <0x60900 0x100>,
+ <0x60b00 0x100>;
xor10 {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -251,26 +413,56 @@
};
};
+ crypto: crypto@90000 {
+ compatible = "inside-secure,safexcel-eip97ies";
+ reg = <0x90000 0x20000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1",
+ "ring2", "ring3", "eip";
+ clocks = <&nb_periph_clk 15>;
+ };
+
+ rwtm: mailbox@b0000 {
+ compatible = "marvell,armada-3700-rwtm-mailbox";
+ reg = <0xb0000 0x100>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
sdhci1: sdhci@d0000 {
compatible = "marvell,armada-3700-sdhci",
- "marvell,sdhci-xenon";
- reg = <0xd0000 0x300
- 0x1e808 0x4>;
+ "marvell,sdhci-xenon";
+ reg = <0xd0000 0x300>,
+ <0x1e808 0x4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 0>;
+ clock-names = "core";
status = "disabled";
};
sdhci0: sdhci@d8000 {
compatible = "marvell,armada-3700-sdhci",
- "marvell,sdhci-xenon";
- reg = <0xd8000 0x300
- 0x17808 0x4>;
+ "marvell,sdhci-xenon";
+ reg = <0xd8000 0x300>,
+ <0x17808 0x4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 0>;
+ clock-names = "core";
status = "disabled";
};
sata: sata@e0000 {
compatible = "marvell,armada-3700-ahci";
- reg = <0xe0000 0x2000>;
+ reg = <0xe0000 0x178>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_periph_clk 1>;
+ phys = <&comphy2 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
@@ -279,72 +471,26 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1d00000 0x10000>, /* GICD */
- <0x1d40000 0x40000>; /* GICR */
- };
-
- eth0: neta@30000 {
- compatible = "marvell,armada-3700-neta";
- reg = <0x30000 0x20>;
- status = "disabled";
- };
-
- eth1: neta@40000 {
- compatible = "marvell,armada-3700-neta";
- reg = <0x40000 0x20>;
- status = "disabled";
- };
-
- i2c0: i2c@11000 {
- compatible = "marvell,armada-3700-i2c";
- reg = <0x11000 0x100>;
- status = "disabled";
- };
-
- spi0: spi@10600 {
- compatible = "marvell,armada-3700-spi";
- reg = <0x10600 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- spi-max-frequency = <50000000>;
- clocks = <&nb_periph_clk 7>;
- status = "disabled";
- };
-
- comphy: comphy@18300 {
- compatible = "marvell,comphy-a3700";
- reg = <0x18300 0x28>,
- <0x1f300 0x3d000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- comphy0: phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- comphy1: phy@1 {
- reg = <1>;
- #phy-cells = <1>;
- };
-
- comphy2: phy@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
+ <0x1d40000 0x40000>, /* GICR */
+ <0x1d80000 0x2000>, /* GICC */
+ <0x1d90000 0x2000>, /* GICH */
+ <0x1da0000 0x20000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
pcie0: pcie@d0070000 {
compatible = "marvell,armada-3700-pcie";
+ device_type = "pci";
+ status = "disabled";
reg = <0 0xd0070000 0 0x20000>;
#address-cells = <3>;
#size-cells = <2>;
- device_type = "pci";
- num-lanes = <1>;
- status = "disabled";
-
- bus-range = <0 0xff>;
+ bus-range = <0x00 0xff>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ msi-parent = <&pcie0>;
+ msi-controller;
/*
* The 128 MiB address range [0xe8000000-0xf0000000] is
* dedicated for PCIe and can be assigned to 8 windows
@@ -352,10 +498,27 @@
* IO at the end and the remaining seven windows
* (totaling 127 MiB) for MEM.
*/
- ranges = <0x82000000 0 0xe8000000
- 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
- 0x81000000 0 0xeff00000
- 0 0xeff00000 0 0x100000>; /* Port 0 IO*/
+ ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
+ 0x81000000 0 0xeff00000 0 0xeff00000 0 0x00100000>; /* Port 0 IO*/
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ max-link-speed = <2>;
+ phys = <&comphy1 0>;
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ firmware {
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware";
+ mboxes = <&rwtm 0>;
+ status = "okay";
};
};
};