arch/arm/dts/armada-37xx.dtsi

/*
 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
 *
 * Copyright (C) 2016 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/comphy/comphy_data.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell Armada 37xx SoC";
	compatible = "marvell,armada3700";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		internal-regs {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			/* 32M internal register @ 0xd000_0000 */
			ranges = <0x0 0x0 0xd0000000 0x2000000>;

			uart0: serial@12000 {
				compatible = "marvell,armada-3700-uart";
				reg = <0x12000 0x400>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			wdt: watchdog-timer@8300 {
				compatible = "marvell,armada-3700-wdt";
				reg = <0x8300 0x40>;
			};

			nb_periph_clk: nb-periph-clk@13000 {
				compatible = "marvell,armada-3700-periph-clock-nb";
				reg = <0x13000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
				#clock-cells = <1>;
			};

			sb_periph_clk: sb-periph-clk@18000 {
				compatible = "marvell,armada-3700-periph-clock-sb";
				reg = <0x18000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
				#clock-cells = <1>;
			};

			tbg: tbg@13200 {
				compatible = "marvell,armada-3700-tbg-clock";
				reg = <0x13200 0x100>;
				#clock-cells = <1>;
			};

			pinctrl_nb: pinctrl-nb@13800 {
				compatible = "marvell,armada3710-nb-pinctrl",
				"syscon", "simple-mfd";
				reg = <0x13800 0x100>, <0x13C00 0x20>;
				gpionb: gpionb {
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_nb 0 0 36>;
					gpio-controller;
					interrupts =
					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

				};

				spi_quad_pins: spi-quad-pins {
					groups = "spi_quad";
					function = "spi";
				};

				i2c1_pins: i2c1-pins {
					groups = "i2c1";
					function = "i2c";
				};

				i2c2_pins: i2c2-pins {
					groups = "i2c2";
					function = "i2c";
				};

				uart1_pins: uart1-pins {
					groups = "uart1";
					function = "uart";
				};

				uart2_pins: uart2-pins {
					groups = "uart2";
					function = "uart";
				};

				mmc_pins: mmc-pins {
					groups = "emmc_nb";
					function = "emmc";
				};
			};

			pinctrl_sb: pinctrl-sb@18800 {
				compatible = "marvell,armada3710-sb-pinctrl",
				"syscon", "simple-mfd";
				reg = <0x18800 0x100>, <0x18C00 0x20>;
				gpiosb: gpiosb {
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_sb 0 0 30>;
					gpio-controller;
					interrupts =
					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
				};

				rgmii_pins: mii-pins {
					groups = "rgmii";
					function = "mii";
				};

				smi_pins: smi-pins {
					groups = "smi";
					function = "smi";
				};

				sdio_pins: sdio-pins {
					groups = "sdio_sb";
					function = "sdio";
				};

				pcie_pins: pcie-pins {
					groups = "pcie1";
					function = "gpio";
				};
			};

			usb3: usb@58000 {
				compatible = "marvell,armada3700-xhci",
				"generic-xhci";
				reg = <0x58000 0x4000>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			usb2: usb@5e000 {
				compatible = "marvell,armada-3700-ehci";
				reg = <0x5e000 0x450>;
				status = "disabled";
			};

			xor@60900 {
				compatible = "marvell,armada-3700-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;

				xor10 {
					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				};
				xor11 {
					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			sdhci1: sdhci@d0000 {
				compatible = "marvell,armada-3700-sdhci",
				"marvell,sdhci-xenon";
				reg = <0xd0000 0x300
				       0x1e808 0x4>;
				status = "disabled";
			};

			sdhci0: sdhci@d8000 {
				compatible = "marvell,armada-3700-sdhci",
				"marvell,sdhci-xenon";
				reg = <0xd8000 0x300
				       0x17808 0x4>;
				status = "disabled";
			};

			sata: sata@e0000 {
				compatible = "marvell,armada-3700-ahci";
				reg = <0xe0000 0x2000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			gic: interrupt-controller@1d00000 {
				compatible = "arm,gic-v3";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x1d00000 0x10000>, /* GICD */
				      <0x1d40000 0x40000>; /* GICR */
			};

			eth0: neta@30000 {
				compatible = "marvell,armada-3700-neta";
				reg = <0x30000 0x20>;
				status = "disabled";
			};

			eth1: neta@40000 {
				compatible = "marvell,armada-3700-neta";
				reg = <0x40000 0x20>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,armada-3700-i2c";
				reg = <0x11000 0x100>;
				status = "disabled";
			};

			spi0: spi@10600 {
				compatible = "marvell,armada-3700-spi";
				reg = <0x10600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				#clock-cells = <0>;
				spi-max-frequency = <50000000>;
				clocks = <&nb_periph_clk 7>;
				status = "disabled";
			};

			comphy: comphy@18300 {
				compatible = "marvell,comphy-a3700";
				reg = <0x18300 0x28>,
				      <0x1f300 0x3d000>;
				#address-cells = <1>;
				#size-cells = <0>;

				comphy0: phy@0 {
					reg = <0>;
					#phy-cells = <1>;
				};

				comphy1: phy@1 {
					reg = <1>;
					#phy-cells = <1>;
				};

				comphy2: phy@2 {
					reg = <2>;
					#phy-cells = <1>;
				};
			};
		};

		pcie0: pcie@d0070000 {
			compatible = "marvell,armada-3700-pcie";
			reg = <0 0xd0070000 0 0x20000>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <1>;
			status = "disabled";

			bus-range = <0 0xff>;
			/*
			 * The 128 MiB address range [0xe8000000-0xf0000000] is
			 * dedicated for PCIe and can be assigned to 8 windows
			 * with size a power of two. Use one 1 MiB window for
			 * IO at the end and the remaining seven windows
			 * (totaling 127 MiB) for MEM.
			 */
			ranges = <0x82000000 0 0xe8000000
				 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
				 0x81000000 0 0xeff00000
				 0 0xeff00000 0 0x100000>; /* Port 0 IO*/
		};
	};
};