arch/arm/dts/rk3588s-u-boot.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
 */

#include "rockchip-u-boot.dtsi"

/ {
	aliases {
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
		spi5 = &sfc;
	};

	dmc {
		compatible = "rockchip,rk3588-dmc";
		bootph-all;
		status = "okay";
	};

	usbdrd3_0: usbdrd3_0 {
		compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
		clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
			 <&cru ACLK_USB3OTG0>;
		clock-names = "ref", "suspend", "bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usbdrd_dwc3_0: usb@fc000000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfc000000 0x0 0x400000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
			power-domains = <&power RK3588_PD_USB>;
			resets = <&cru SRST_A_USB3OTG0>;
			reset-names = "usb3-otg";
			dr_mode = "otg";
			phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
			phy-names = "usb2-phy", "usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			quirk-skip-phy-init;
		};
	};

	pmu1_grf: syscon@fd58a000 {
		bootph-all;
		compatible = "rockchip,rk3588-pmu1-grf", "syscon";
		reg = <0x0 0xfd58a000 0x0 0x2000>;
	};

	usb2phy0_grf: syscon@fd5d0000 {
		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
			     "simple-mfd";
		reg = <0x0 0xfd5d0000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;

		u2phy0: usb2-phy@0 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0x0 0x10>;
			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
			resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
			reset-names = "phy", "apb";
			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
			clock-names = "phyclk";
			clock-output-names = "usb480m_phy0";
			#clock-cells = <0>;
			rockchip,usbctrl-grf = <&usb_grf>;
			status = "disabled";

			u2phy0_otg: otg-port {
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	vo0_grf: syscon@fd5a6000 {
		compatible = "rockchip,rk3588-vo-grf", "syscon";
		reg = <0x0 0xfd5a6000 0x0 0x2000>;
		clocks = <&cru PCLK_VO0GRF>;
	};

	usb_grf: syscon@fd5ac000 {
		compatible = "rockchip,rk3588-usb-grf", "syscon";
		reg = <0x0 0xfd5ac000 0x0 0x4000>;
	};

	usbdpphy0_grf: syscon@fd5c8000 {
		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
		reg = <0x0 0xfd5c8000 0x0 0x4000>;
	};

	rng: rng@fe378000 {
		compatible = "rockchip,trngv1";
		reg = <0x0 0xfe378000 0x0 0x200>;
		status = "disabled";
	};

	usbdp_phy0: phy@fed80000 {
		compatible = "rockchip,rk3588-usbdp-phy";
		reg = <0x0 0xfed80000 0x0 0x10000>;
		rockchip,u2phy-grf = <&usb2phy0_grf>;
		rockchip,usb-grf = <&usb_grf>;
		rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
		rockchip,vo-grf = <&vo0_grf>;
		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
			 <&cru CLK_USBDP_PHY0_IMMORTAL>,
			 <&cru PCLK_USBDPPHY0>,
			 <&u2phy0>;
		clock-names = "refclk", "immortal", "pclk", "utmi";
		resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
			 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
			 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
			 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
			 <&cru SRST_P_USBDPPHY0>;
		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
		status = "disabled";

		usbdp_phy0_dp: dp-port {
			#phy-cells = <0>;
			status = "disabled";
		};

		usbdp_phy0_u3: usb3-port {
			#phy-cells = <0>;
			status = "disabled";
		};
	};
};

&emmc_bus8 {
	bootph-all;
};

&emmc_clk {
	bootph-all;
};

&emmc_cmd {
	bootph-all;
};

&emmc_data_strobe {
	bootph-all;
};

&emmc_rstnout {
	bootph-all;
};

&pinctrl {
	bootph-all;
};

&pcfg_pull_none {
	bootph-all;
};

&pcfg_pull_up_drv_level_2 {
	bootph-all;
};

&pcfg_pull_up {
	bootph-all;
};

&xin24m {
	bootph-all;
	status = "okay";
};

&cru {
	bootph-pre-ram;
	status = "okay";
};

&sys_grf {
	bootph-pre-ram;
	status = "okay";
};

&scmi {
	bootph-pre-ram;
};

&scmi_clk {
	bootph-pre-ram;
};

&sdmmc {
	bootph-pre-ram;
	u-boot,spl-fifo-mode;
};

&sdhci {
	bootph-pre-ram;
	u-boot,spl-fifo-mode;
};

&sdmmc_bus4 {
	bootph-all;
};

&sdmmc_clk {
	bootph-all;
};

&sdmmc_cmd {
	bootph-all;
};

&sdmmc_det {
	bootph-all;
};

&uart2 {
	clock-frequency = <24000000>;
	bootph-pre-ram;
	status = "okay";
};

&uart2m0_xfer {
	bootph-all;
};

&ioc {
	bootph-pre-ram;
};

#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
&binman {
	simple-bin-spi {
		mkimage {
			args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
			offset = <0x8000>;
		};
	};
};
#endif