| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Qualcomm QCS404 memory map |
| * |
| * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> |
| */ |
| |
| #include <common.h> |
| #include <asm/armv8/mmu.h> |
| |
| static struct mm_region qcs404_mem_map[] = { |
| { |
| .virt = 0x0UL, /* Peripheral block */ |
| .phys = 0x0UL, /* Peripheral block */ |
| .size = 0x8000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| .virt = 0x80000000UL, /* DDR */ |
| .phys = 0x80000000UL, /* DDR */ |
| .size = 0x05900000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x89600000UL, /* DDR */ |
| .phys = 0x89600000UL, /* DDR */ |
| .size = 0x162000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0xa0000000UL, /* DDR */ |
| .phys = 0xa0000000UL, /* DDR */ |
| .size = 0x20000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| /* List terminator */ |
| 0, |
| } |
| }; |
| |
| struct mm_region *mem_map = qcs404_mem_map; |