| # SPDX-License-Identifier: GPL-2.0+ |
| # |
| # Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> |
| # |
| |
| config CLK_TI_AM3_DPLL |
| bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers" |
| depends on CLK && OF_CONTROL |
| help |
| This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL |
| provides all interface clocks and functional clocks to the processor. |
| |
| config CLK_TI_CTRL |
| bool "TI OMAP4 clock controller" |
| depends on CLK && OF_CONTROL |
| help |
| This enables the clock controller driver support on TI's SoCs. |
| |
| config CLK_TI_DIVIDER |
| bool "TI divider clock driver" |
| depends on CLK && OF_CONTROL && CLK_CCF |
| help |
| This enables the divider clock driver support on TI's SoCs. |
| |
| config CLK_TI_GATE |
| bool "TI gate clock driver" |
| depends on CLK && OF_CONTROL |
| help |
| This enables the gate clock driver support on TI's SoCs. |
| |
| config CLK_TI_MUX |
| bool "TI mux clock driver" |
| depends on CLK && OF_CONTROL && CLK_CCF |
| help |
| This enables the mux clock driver support on TI's SoCs. |