arch/arm/dts/rk3588.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
 */

#include "rk3588s.dtsi"
#include "rk3588-pinctrl.dtsi"

/ {
	i2s8_8ch: i2s@fddc8000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfddc8000 0x0 0x1000>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac2 22>;
		dma-names = "tx";
		power-domains = <&power RK3588_PD_VO0>;
		resets = <&cru SRST_M_I2S8_8CH_TX>;
		reset-names = "tx-m";
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s6_8ch: i2s@fddf4000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfddf4000 0x0 0x1000>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac2 4>;
		dma-names = "tx";
		power-domains = <&power RK3588_PD_VO1>;
		resets = <&cru SRST_M_I2S6_8CH_TX>;
		reset-names = "tx-m";
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s7_8ch: i2s@fddf8000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfddf8000 0x0 0x1000>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac2 21>;
		dma-names = "rx";
		power-domains = <&power RK3588_PD_VO1>;
		resets = <&cru SRST_M_I2S7_8CH_RX>;
		reset-names = "rx-m";
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s10_8ch: i2s@fde00000 {
		compatible = "rockchip,rk3588-i2s-tdm";
		reg = <0x0 0xfde00000 0x0 0x1000>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
		assigned-clock-parents = <&cru PLL_AUPLL>;
		dmas = <&dmac2 24>;
		dma-names = "rx";
		power-domains = <&power RK3588_PD_VO1>;
		resets = <&cru SRST_M_I2S10_8CH_RX>;
		reset-names = "rx-m";
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	gmac0: ethernet@fe1b0000 {
		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
		reg = <0x0 0xfe1b0000 0x0 0x10000>;
		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "macirq", "eth_wake_irq";
		clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
			 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
			 <&cru CLK_GMAC0_PTP_REF>;
		clock-names = "stmmaceth", "clk_mac_ref",
			      "pclk_mac", "aclk_mac",
			      "ptp_ref";
		power-domains = <&power RK3588_PD_GMAC>;
		resets = <&cru SRST_A_GMAC0>;
		reset-names = "stmmaceth";
		rockchip,grf = <&sys_grf>;
		rockchip,php-grf = <&php_grf>;
		snps,axi-config = <&gmac0_stmmac_axi_setup>;
		snps,mixed-burst;
		snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
		snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
		snps,tso;
		status = "disabled";

		mdio0: mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		gmac0_stmmac_axi_setup: stmmac-axi-config {
			snps,blen = <0 0 0 0 16 8 4>;
			snps,wr_osr_lmt = <4>;
			snps,rd_osr_lmt = <8>;
		};

		gmac0_mtl_rx_setup: rx-queues-config {
			snps,rx-queues-to-use = <2>;
			queue0 {};
			queue1 {};
		};

		gmac0_mtl_tx_setup: tx-queues-config {
			snps,tx-queues-to-use = <2>;
			queue0 {};
			queue1 {};
		};
	};
};